EGGH03: SIGGRAPH/Eurographics Workshop on Graphics Hardware 2003

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https://diglib.eg.org/handle/10.2312/332

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Browsing EGGH03: SIGGRAPH/Eurographics Workshop on Graphics Hardware 2003 by Subject "I.3.7 [Computer Graphics]"

Now showing 1 - 6 of 6
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    Automatic Shader Level of Detail
    (The Eurographics Association, 2003) Olano, Marc; Kuehne, Bob; Simmons, Maryann; M. Doggett and W. Heidrich and W. Mark and A. Schilling
    Current graphics hardware can render procedurally shaded objects in real-time. However, due to resource and performance limitations, interactive shaders can not yet approach the complexity of shaders written for film production and software rendering, which may stretch to thousands of lines. These constraints limit not only the complexity of a single shader, but also the number of shaded objects that can be rendered at interactive rates. This problem has many similarities to the rendering of large models, the source of extensive research in geometric simplification and level of detail. We introduce an analogous process for shading : shader simplification. Starting from an initial detailed shader, shader simplification automatically produces a set of simplified shaders or a single new shader with extra level-of-detail parameters that control the shader execution. The resulting level-of-detail shader can automatically adjust its rendered appearance based on measures of distance, size, or importance, as well as physical limits such as rendering time budget or texture usage. We demonstrate shader simplification with a system that automatically creates shader levels of detail to reduce the number of texture accesses, one common limiting factor for current hardware.
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    An Effective Hardware Architecture for Bump Mapping Using Angular Operation
    (The Eurographics Association, 2003) Lee, S. G.; Park, W. C.; Lee, W. J.; Han, T. D.; Yang, S. B.; M. Doggett and W. Heidrich and W. Mark and A. Schilling
    In this paper, we propose an effective bump mapping algorithm that utilizes the reference space with the polar coordinate system and also propose a new hardware architecture associated with the proposed bump mapping algorithm. The proposed architecture reduces the computations to transform the vectors from the object space into the reference space by using a new vector rotation method. It also reduces the computations for the illumination calculation by using the law of cosine. Compared with the previous approaches, the proposed architecture reduces multiplication operations up to 78%.
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    An Optimized Soft Shadow Volume Algorithm with Real-Time Performance
    (The Eurographics Association, 2003) Assarsson, Ulf; Dougherty, Michael; Mounier, Michael; Akenine-Möller, Tomas; M. Doggett and W. Heidrich and W. Mark and A. Schilling
    In this paper, we present several optimizations to our previously presented soft shadow volume algorithm. Our optimizations include tighter wedges, heavily optimized pixel shader code for both rectangular and spherical light sources, a frame buffer blending technique to overcome the limitation of 8-bit frame buffers, and a simple culling algorithm. These together give real-time performance, and for simple models we get frame rates of over 150 fps. For more complex models 50 fps is normal. In addition to optimizations, two simple techniques for improving the visual quality are also presented.
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    Photon Mapping on Programmable Graphics Hardware
    (The Eurographics Association, 2003) Purcell, Timothy J.; Donner, Craig; Cammarano, Mike; Jensen, Henrik Wann; Hanrahan, Pat; M. Doggett and W. Heidrich and W. Mark and A. Schilling
    We present a modified photon mapping algorithm capable of running entirely on GPUs. Our implementation uses breadth-first photon tracing to distribute photons using the GPU. The photons are stored in a grid-based photon map that is constructed directly on the graphics hardware using one of two methods: the first method is a multipass technique that uses fragment programs to directly sort the photons into a compact grid. The second method uses a single rendering pass combining a vertex program and the stencil buffer to route photons to their respective grid cells, producing an approximate photon map. We also present an efficient method for locating the nearest photons in the grid, which makes it possible to compute an estimate of the radiance at any surface location in the scene. Finally, we describe a breadth-first stochastic ray tracer that uses the photon map to simulate full global illumination directly on the graphics hardware. Our implementation demonstrates that current graphics hardware is capable of fully simulating global illumination with progressive, interactive feedback to the user.
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    Texture Compression using Low-Frequency Signal Modulation
    (The Eurographics Association, 2003) Fenney, Simon; M. Doggett and W. Heidrich and W. Mark and A. Schilling
    This paper presents a new, lossy texture compression technique that is suited to implementation on low-cost, low-bandwidth devices as well as more powerful rendering systems. It uses a representation that is based on the blending of two (or more) `low frequency' signals using a high frequency but low precision modulation signal. Continuity of the low frequency signals helps to avoid block artefacts. Decompression costs are kept low through use of fixed-rate encoding and by eliminating indirect data access, as needed with Vector Quantisation schemes. Good quality reproduction of (A)RGB textures is achieved with a choice of 4bpp or 2bpp representations.
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    VoxelCache: A Cache-Based Memory Architecture for Volume Graphics
    (The Eurographics Association, 2003) Kanus, U.; Wetekam, G.; Hirche, J.; M. Doggett and W. Heidrich and W. Mark and A. Schilling
    This paper presents a cache-based memory architecture for volume graphics. We describe the memory organization and cache logic to implement a voxel cache based on 43 voxel blocks. We show an efficient prefetching scheme that increases the cache hit ratio to more than 98% in most cases. The performance of the memory system with different types of external memory is demonstrated by a cycle accurate C++ simulation. The VoxelCache memory architecture is designed to be easily adapted to different memory technologies, because all volume graphics specific parts of the memory system are encapsulated inside the on-chip cache. The design is targeted at implementation on off-the-shelf reconfigurable hardware.