Hexagonal Storage Scheme for Interleaved Frame Buffers and Textures

Simple item page
dc.contributor.authorBando, Yosukeen_US
dc.contributor.authorSaito, Takahiroen_US
dc.contributor.authorFujita, Masahiroen_US
dc.contributor.editorMichael Meissner and Bengt-Olaf Schneideren_US
dc.date.accessioned2013-10-28T10:03:36Z
dc.date.available2013-10-28T10:03:36Z
dc.date.issued2005en_US
dc.description.abstractThis paper presents a storage scheme which statically assigns pixel/texel coordinates to multiple memory banks in order to minimize frame buffer and texture memory access load imbalance. In this scheme, the pixels stored in a particular memory bank are placed at the center and the vertices of hexagons packed in the frame buffer. By making these hexagons close to regular so that the pixel placement is uniform and isotropic, frame buffer and texture memory accesses are evenly distributed over the memory banks. The analysis of memory access patterns in rendering typical 3D graphics scenes shows that the hexagonal storage scheme can reduce rendering performance degradation due to bank conflicts by an average of 10% compared to the traditional rectangular storage scheme.en_US
dc.description.seriesinformationGraphics Hardwareen_US
dc.identifier.isbn1-59593-086-8en_US
dc.identifier.issn1727-3471en_US
dc.identifier.urihttps://doi.org/10.2312/EGGH/EGGH05/033-040en_US
dc.publisherThe Eurographics Associationen_US
dc.subjectCategories and Subject Descriptors (according to ACM CCS): I.3.1 [Computer Graphics]: Parallel Processingen_US
dc.titleHexagonal Storage Scheme for Interleaved Frame Buffers and Texturesen_US
Files
Collections
EGGH05: SIGGRAPH/Eurographics Workshop on Graphics Hardware 2005