A VLSI Chip for Ray Tracing Bicubic Patches

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dc.contributor.authorBouatouch, Kadien_US
dc.contributor.authorSaouter, Yannicken_US
dc.contributor.authorCandela, Jean Charlesen_US
dc.date.accessioned2015-10-05T07:56:07Z
dc.date.available2015-10-05T07:56:07Z
dc.date.issued1989en_US
dc.description.abstractThis paper deals with the integration of a VLSI chip dedicated to ray tracing bicubic patches. A recursive subdivision algorithm is embedded in this chip. The recursion stops when the termination conditions are met. A software implementation allowed for the determination of key parameters which influenced the choice of the proposed chip' architecture. Only some modules of the chip are, at the present time, simulated and laid out, the rest is being implemented. A detailed description of the chip' modules is given.en_US
dc.description.seriesinformationEG 1989-Technical Papersen_US
dc.identifier.doi10.2312/egtp.19891008en_US
dc.identifier.issn1017-4656en_US
dc.identifier.urihttps://doi.org/10.2312/egtp.19891008en_US
dc.publisherEurographics Associationen_US
dc.titleA VLSI Chip for Ray Tracing Bicubic Patchesen_US
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