A Reconfigurable Architecture for Load-Balanced Rendering

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dc.contributor.authorChen, Jiawenen_US
dc.contributor.authorGordon, Michael I.en_US
dc.contributor.authorThies, Williamen_US
dc.contributor.authorZwicker, Matthiasen_US
dc.contributor.authorPulli, Karien_US
dc.contributor.authorDurand, Frédoen_US
dc.contributor.editorMichael Meissner and Bengt-Olaf Schneideren_US
dc.date.accessioned2013-10-28T10:03:38Z
dc.date.available2013-10-28T10:03:38Z
dc.date.issued2005en_US
dc.description.abstractCommodity graphics hardware has become increasingly programmable over the last few years but has been limited to fixed resource allocation. These architectures handle some workloads well, others poorly; load-balancing to maximize graphics hardware performance has become a critical issue. In this paper, we explore one solution to this problem using compile-time resource allocation. For our experiments, we implement a graphics pipeline on Raw, a tile-based multicore processor. We express both the full graphics pipeline and the shaders using StreamIt, a high-level language based on the stream programming model. The programmer specifies the number of tiles per pipeline stage, and the StreamIt compiler maps the computation to the Raw architecture. We evaluate our reconfigurable architecture using a mix of common rendering tasks with different workloads and improve throughput by 55-157% over a static allocation. Although our early prototype cannot compete in performance against commercial state-of-the-art graphics processors, we believe that this paper describes an important first step in addressing the load-balancing challenge.en_US
dc.description.seriesinformationGraphics Hardwareen_US
dc.identifier.isbn1-59593-086-8en_US
dc.identifier.issn1727-3471en_US
dc.identifier.urihttps://doi.org/10.2312/EGGH/EGGH05/071-080en_US
dc.publisherThe Eurographics Associationen_US
dc.subjectCategories and Subject Descriptors (according to ACM CCS): I.3.1 [Computer Graphics]: Hardware Architecture - Graphics processors C.1.2 [Processor Architectures]: Multiple Data Stream Architectures - Single-instructionstream, multiple-data-stream processors (SIMD)en_US
dc.titleA Reconfigurable Architecture for Load-Balanced Renderingen_US
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EGGH05: SIGGRAPH/Eurographics Workshop on Graphics Hardware 2005