Prefetching in a Texture Cache Architecture
| dc.contributor.author | lgehy, Homan | en_US |
| dc.contributor.author | Eldridge, Matthew | en_US |
| dc.contributor.author | Proudfoot, Kekoa | en_US |
| dc.contributor.editor | S. N. Spencer | en_US |
| dc.date.accessioned | 2014-02-06T15:01:29Z | |
| dc.date.available | 2014-02-06T15:01:29Z | |
| dc.date.issued | 1998 | en_US |
| dc.description.abstract | Texture mapping has become so ubiquitous in real-time graphics hardware that many systems are able to perform filtered texturing without any penalty in fill rate. The computation rates available in hardware have been outpacing the memory access rates, and texture systems are becoming constrained by memory bandwidth and latency. Caching in conjunction with prefetching can be used to alleviate this problem. In this paper, WC introduce a prefetching texture cache architecture designed to take advantage of the access characteristics of texture mapping. The structures needed are relatively simple and arc amenable to high clock rates. To quantify the robustness of our architecture, we identify a set of six scenes whose texture locality varies over nearly two orders of magnitude and a set 01 four memory systems with varying bandwidths and latencies. Through the use of a cycle-accurate simulation, we demonstrate that even in the presence of a high-latency memory system, our architecture can attain at least 97% of the performance of a zerolatency memory system. | en_US |
| dc.description.seriesinformation | SIGGRAPH/Eurographics Workshop on Graphics Hardware | en_US |
| dc.identifier.isbn | 0-89791-097-X | en_US |
| dc.identifier.issn | 1727-3471 | en_US |
| dc.identifier.uri | https://doi.org/10.2312/EGGH/EGGH98/133-142 | en_US |
| dc.publisher | The Eurographics Association | en_US |
| dc.subject | 1.3.1 [Computer Graphics] | en_US |
| dc.subject | Hardware Architecture | en_US |
| dc.title | Prefetching in a Texture Cache Architecture | en_US |
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