AVLSI Chip for Ray Tracing Bicubic Patches
| dc.contributor.author | Pulleyblank, R W. | en_US |
| dc.contributor.author | Kapenga, J. | en_US |
| dc.contributor.editor | W. Strasser | en_US |
| dc.date.accessioned | 2014-02-06T13:58:14Z | |
| dc.date.available | 2014-02-06T13:58:14Z | |
| dc.date.issued | 1986 | en_US |
| dc.description.abstract | A VLSI chip for ray tracing bicubic patches in Bezier form is explored. The purpose of the chip is to calculate the intersection point of a ray with the bicubic patch to a specified level of accuracy, returning the location of the intersection on the patch and on the ray. This is done by computing the intersection of the ray with a bounding volume of the patch and repeatedly subdividing the patch until the bounding volume of subpatches hit by the ray is smaller than the accuracy requirement. There are two operating modes, one in which only the nearest intersection is found and another in which all intersections are found. This algorithm correctly handles rays tangentially intersecting a planar patch and ray intersections at a silhouette edge of the patch. Estimates indicate that such a chip could be implemented in 2 micron NMOS and could compute patch/ray intersections at the rate of one every 15 microseconds for patches that are prescaled and specified to 12 bits fixed point for each of the x, y and z components. A version capable of handling 24 bit patches could compute patch/ray intersections at the rate of one every 140 microseconds. Images drawn using a software version of the algorithm are presented and discussed. | en_US |
| dc.description.seriesinformation | Eurographics workshop on Graphics Hardware | en_US |
| dc.identifier.isbn | 3-540-18222-5 | en_US |
| dc.identifier.issn | 1727-3471 | en_US |
| dc.identifier.uri | https://doi.org/10.2312/EGGH/EGGH86/125-140 | en_US |
| dc.publisher | The Eurographics Association | en_US |
| dc.title | AVLSI Chip for Ray Tracing Bicubic Patches | en_US |
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