VLSI Drawing Processor Utilizing Multiple ParallelScan-Line Processors

dc.contributor.authorDenault, Damianen_US
dc.contributor.authorRyherd, Ericen_US
dc.contributor.authorTorborg, Johnen_US
dc.contributor.editorFons Kuijk and Wolfgang Strasseren_US
dc.date.accessioned2014-02-06T14:01:47Z
dc.date.available2014-02-06T14:01:47Z
dc.date.issued1987en_US
dc.description.abstractIn a typical graphics system, a single drawing processor is used to perform pixel level drawing operations, one pixel at a time. A VLSI based drawing processor and image memory controller is presented which takes advantage of scan-line partitioning of many graphics operations. A four processor implementation is described which operates on four scan-lines in parallel to achieve near real-time shading performance for complex objects. Drawing processor commands are provided for points, vectors, triangles, rectangles, block pixel moves, and image transfers. Vectors and triangles can be drawn with shading and depth buffering. The chips also incorporate integral vector and area pattern registers, and support translucency. The drawing processor chips directly interface to the image memory RAMs without any external buffers, registers, caches, or control logic, allowing a high performance system to be configured simply and cost effectively. These chips are implemented in the GX4000 high performance workstation graphics system which is capable of rendering close to 200,000 shaded and depth-buffered 100 pixel polygons per second and over 34,000 shaded and depth-buffered 1000 pixel polygons per second.en_US
dc.description.seriesinformationEurographics Workshop on Graphics Hardwareen_US
dc.identifier.isbn3-540-50109-6en_US
dc.identifier.issn1727-3471en_US
dc.identifier.urihttps://doi.org/10.2312/EGGH/EGGH87/167-182en_US
dc.publisherThe Eurographics Associationen_US
dc.subjectinterpolationen_US
dc.subjectscan conversionen_US
dc.subjectshadingen_US
dc.subjectimage synthesisen_US
dc.subjectgraphics VLSIen_US
dc.subjectframe buffer controlen_US
dc.titleVLSI Drawing Processor Utilizing Multiple ParallelScan-Line Processorsen_US
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