Architectural Implications of Hardware-Accelerated Bucket Rendering on the PC

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dc.contributor.authorCox, Michaelen_US
dc.contributor.authorBhandari, Narendraen_US
dc.contributor.editorA. Kaufmann and W. Strasser and S. Molnar and B.-O. Schneideren_US
dc.date.accessioned2014-02-06T14:56:59Z
dc.date.available2014-02-06T14:56:59Z
dc.date.issued1997en_US
dc.description.abstractBucket rendering is a technique whereby a scene is sorted into screen-space tiles and each tile is rendered independently in turn. We expect hardware-accelerated bucket rendering to become available on the PC, and in this paper we explore the effect of such accelerators on main memory bandwidth, bus bandwidth to the accelerator, and on increased triangle set-up requirements. The most important impact is due to the fact that in general primitives overlap multiple buckets, which is a direct cause of overhead. In this paper we evaluate bucket rendering that uses the most common algorithm for bucket sorting, one based on screen-aligned primitive bounding boxes. We extend previous techniques for analytically evaluating bounding box overlap of buckets, and together with experimental results use these to evaluate accelerators that may support 32x32 pixel tiles, and those that may support 128x128 pixel tiles. We expect the former to be possible with dense SRAM, the latter to be possible with DRAM embedded in a logic process (embedded DRAM). Our results suggest that embedded DRAM implementations can support bucket rendering with bounding box bucket sorting, but that SRAM implementations will likely be at risk with respect to overall system performance when bounding box bucket sorting is employed. These results suggest the requirement for more precise but still low-overhead bucket sorting algorithms when bucket rendering hardware is constrained to 32 x 32 tiles.en_US
dc.description.seriesinformationSIGGRAPH/Eurographics Workshop on Graphics Hardwareen_US
dc.identifier.isbn0-89791-961-0en_US
dc.identifier.issn1727-3471en_US
dc.identifier.urihttps://doi.org/10.2312/EGGH/EGGH97/025-033en_US
dc.publisherThe Eurographics Associationen_US
dc.subject13.1 [Computer Graphics]en_US
dc.subjectHardware Architectureen_US
dc.subjectraster display devicesen_US
dc.subject1.33 [Computer Graphics]en_US
dc.subjectPictur/Image Generationen_US
dc.subjectdisplay algorithmsen_US
dc.subjectL3.7 [Computer Graphics]en_US
dc.subjectThree Dimensional Graphics and Realismen_US
dc.subjectvisible surface algorithms.en_US
dc.titleArchitectural Implications of Hardware-Accelerated Bucket Rendering on the PCen_US
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EGGH97: SIGGRAPH/Eurographics Workshop on Graphics Hardware 1997