A Hardware-Friendly Bilateral Solver Accelerator for Real-Time Virtual Reality Video
dc.contributor.author | Mazumdar, Amrita | en_US |
dc.contributor.author | Alaghi, Armin | en_US |
dc.contributor.author | Barron, Jonathan T. | en_US |
dc.contributor.author | Gallup, David | en_US |
dc.contributor.author | Ceze, Luis | en_US |
dc.contributor.author | Oskin, Mark | en_US |
dc.contributor.author | Seitz, Steven M. | en_US |
dc.contributor.editor | Vlastimil Havran and Karthik Vaiyanathan | en_US |
dc.date.accessioned | 2017-12-06T19:47:35Z | |
dc.date.available | 2017-12-06T19:47:35Z | |
dc.date.issued | 2017 | |
dc.description.abstract | Rendering 3D-360° VR video from a camera rig is computationintensive and typically performed o ine. In this paper, we target the most time-consuming step of the VR video creation process, high-quality ow estimation with the bilateral solver.We propose a new algorithm, the hardware-friendly bilateral solver, that enables faster runtimes than existing algorithms of similar quality. Our algorithm is easily parallelized, achieving a 4 speedup on CPU and 32 speedup on GPU over a baseline CPU implementation. We also design an FPGA-based hardware accelerator that utilizes reduced-precision computation and the parallelism inherent in our algorithm to achieve further speedups over our CPU and GPU implementations while consuming an order of magnitude less power. e FPGA design's power e ciency enables practical real-time VR video processing at the camera rig or in the cloud. | en_US |
dc.description.sectionheaders | Specialized Hardware Architectures | |
dc.description.seriesinformation | Eurographics/ ACM SIGGRAPH Symposium on High Performance Graphics | |
dc.identifier.doi | 10.1145/3105762.3105772 | |
dc.identifier.isbn | 978-1-4503-5101-0 | |
dc.identifier.issn | 2079-8679 | |
dc.identifier.uri | https://doi.org/10.1145/3105762.3105772 | |
dc.identifier.uri | https://diglib.eg.org:443/handle/10.1145/3105762-3105772 | |
dc.publisher | ACM | en_US |
dc.subject | Hardware Hardware accelerators | |
dc.subject | Computing methodologies Graphics processors | |
dc.subject | Virtual reality | |
dc.subject | Hardware accelerators | |
dc.subject | parallelism | |
dc.subject | FPGA design | |
dc.subject | GPU algorithm | |
dc.subject | real | |
dc.subject | time image processing | |
dc.subject | virtual reality. | |
dc.title | A Hardware-Friendly Bilateral Solver Accelerator for Real-Time Virtual Reality Video | en_US |