Multi-Resolution Meshes for Feature-Aware Hardware Tessellation

Simple item page
dc.contributor.authorLambert, Thibauden_US
dc.contributor.authorBénard, Pierreen_US
dc.contributor.authorGuennebaud, Gaëlen_US
dc.contributor.editorJoaquim Jorge and Ming Linen_US
dc.date.accessioned2016-04-26T08:38:24Z
dc.date.available2016-04-26T08:38:24Z
dc.date.issued2016en_US
dc.description.abstractHardware tessellation is de facto the preferred mechanism to adaptively control mesh resolution with maximal performances. However, owing to its fixed and uniform pattern, leveraging tessellation for feature-aware LOD rendering remains a challenging problem. We relax this fundamental constraint by introducing a new spatial and temporal blending mechanism of tessellation levels, which is built on top of a novel hierarchical representation of multi-resolution meshes. This mechanism allows to finely control topological changes so that vertices can be removed or added at the most appropriate location to preserve geometric features in a continuous and artifact-free manner. We then show how to extend edge-collapse based decimation methods to build feature-aware multi-resolution meshes that match the tessellation patterns. Our approach is fully compatible with current hardware tessellators and only adds a small overhead on memory consumption and tessellation cost.en_US
dc.description.number2en_US
dc.description.sectionheadersMeshesen_US
dc.description.seriesinformationComputer Graphics Forumen_US
dc.description.volume35en_US
dc.identifier.doi10.1111/cgf.12828en_US
dc.identifier.issn1467-8659en_US
dc.identifier.pages253-262en_US
dc.identifier.urihttps://doi.org/10.1111/cgf.12828en_US
dc.publisherThe Eurographics Association and John Wiley & Sons Ltd.en_US
dc.titleMulti-Resolution Meshes for Feature-Aware Hardware Tessellationen_US
Files
Collections
35-Issue 2
EG 2016 - Full Papers - CGF 35-Issue 2