Comparing Reyes and OpenGL on a Stream Architecture
| dc.contributor.author | Owens, John D. | en_US |
| dc.contributor.author | Khailany, Brucek | en_US |
| dc.contributor.author | Towles, Brian | en_US |
| dc.contributor.author | Dally, William J. | en_US |
| dc.contributor.editor | Thomas Ertl and Wolfgang Heidrich and Michael Doggett | en_US |
| dc.date.accessioned | 2013-10-28T10:00:20Z | |
| dc.date.available | 2013-10-28T10:00:20Z | |
| dc.date.issued | 2002 | en_US |
| dc.description.abstract | The OpenGL and Reyes rendering pipelines each render complex scenes from similar scene descriptions but differ in their internal pipeline organizations. While the OpenGL organization has dominated hardware architectures over the past twenty years, a Reyes organization differs in several important ways from OpenGL, including a shader coordinate system that supports coherent texture accesses, a single shader in the vertex stage, and tessellation and sampling instead of triangle rasterization. Hardware for the OpenGL pipeline has been well-studied, but the lack of a hardware Reyes implementation has prevented a comparison between the two pipelines. We analyze and compare implementations of an OpenGL and a Reyes pipeline on the Imagine stream processor, a high performance programmable processor for media applications. This comparison both demonstrates the applicability of Reyes for hardware implementation and exposes many issues that architects will face in implementing Reyes in hardware, in particular the need for efficient subdivision algorithms and implementations. | en_US |
| dc.description.seriesinformation | SIGGRAPH/Eurographics Workshop on Graphics Hardware | en_US |
| dc.identifier.isbn | 1-58113-580-1 | en_US |
| dc.identifier.issn | 1727-3471 | en_US |
| dc.identifier.uri | https://doi.org/10.2312/EGGH/EGGH02/047-056 | en_US |
| dc.publisher | The Eurographics Association | en_US |
| dc.subject | I.3.1 [Computer Graphics] | en_US |
| dc.subject | Hardware Architecture | en_US |
| dc.subject | Graphics Processors | en_US |
| dc.subject | C.1.2 [Processor Architectures] | en_US |
| dc.subject | Multiple Data Stream Architectures | en_US |
| dc.subject | Single | en_US |
| dc.subject | instructionstream | en_US |
| dc.subject | multiple | en_US |
| dc.subject | data | en_US |
| dc.subject | stream processors (SIMD). | en_US |
| dc.title | Comparing Reyes and OpenGL on a Stream Architecture | en_US |