A Hardware Processing Unit for Point Sets
| dc.contributor.author | Heinzle, Simon | en_US |
| dc.contributor.author | Guennebaud, Gaƫl | en_US |
| dc.contributor.author | Botsch, Mario | en_US |
| dc.contributor.author | Gross, Markus | en_US |
| dc.contributor.editor | David Luebke and John Owens | en_US |
| dc.date.accessioned | 2013-10-28T10:19:24Z | |
| dc.date.available | 2013-10-28T10:19:24Z | |
| dc.date.issued | 2008 | en_US |
| dc.description.abstract | We present a hardware architecture and processing unit for point sampled data. Our design is focused on fundamental and computationally expensive operations on point sets including k-nearest neighbors search, moving least squares approximation, and others. Our architecture includes a configurable processing module allowing users to implement custom operators and to run them directly on the chip. A key component of our design is the spatial search unit based on a kd-tree performing both kNN and eN searches. It utilizes stack recursions and features a novel advanced caching mechanism allowing direct reuse of previously computed neighborhoods for spatially coherent queries. In our FPGA prototype, both modules are multi-threaded, exploit full hardware parallelism, and utilize a fixed-function data path and control logic for maximum throughput and minimum chip surface. A detailed analysis demonstrates the performance and versatility of our design. | en_US |
| dc.description.seriesinformation | Graphics Hardware | en_US |
| dc.identifier.isbn | 978-3-905674-09-5 | en_US |
| dc.identifier.issn | 1727-3471 | en_US |
| dc.identifier.uri | https://doi.org/10.2312/EGGH/EGGH08/021-031 | en_US |
| dc.publisher | The Eurographics Association | en_US |
| dc.subject | Categories and Subject Descriptors (according to ACM CCS): I.3.1 [Hardware Architecture]: Graphics processors | en_US |
| dc.title | A Hardware Processing Unit for Point Sets | en_US |
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