EGGH88: Eurographics Workshop on Graphics Hardware 1988

Permanent URI for this collection

https://diglib7.eg.org/handle/10.2312/347

Browse

Now showing 1 - 13 of 13

PROOF: An Architecture for Rendering In Object Space
(The Eurographics Association, 1988) Schneider, Bengt-Olaf; Claussen, Ute; A. A. M.Kuijk
This paper gives a short introduction into the field of computer image generation in hardware. It discusses the two main approaches, namely partitioning in Image space and In object space. Based on the object space partitioning approach we have defined the PROOF architecture. PROOF is a system that aims at high performance and high quality rendering of raster images. high performance means that up to 30 pictures are generated in one second. The pictures are shaded and anti-allased, giving the images a high degree of realism. The architecture comprises tnree stages which are responsible for hidden surface removal, shading, and filtering respectively. The first of these stages a pipeline of object processors. Each of these processors stores and scan converts one obiect Furthermore, It interpolates the depth and the normal vector across the Object. Each object processor IS able to handle objects of a certain primitive type. The specialization of an object processor to a certain primitive type is encapsulated in a Single block called primitive processor. The Outout of the object processor pipeline is the input to a stage for shading. The illumination model employed takes In~o account both diffuse and specular reflections. The paper reviews Gouraud and Phong shading with regard to their suitability for a hardware implementation. The final stage of the PROOF system is formed by a stage for filtering the colours of those objects that contribute to a pixel. This done by constructing a subpixel mask and filtering across an area of 2x2 pixels. At the end. the paper briefly reports on the current state of the project.
Parallel Processing on a Transputer-based Graphics Board
(The Eurographics Association, 1988) Pereira, Joijo; Reis, Francisco; Vinagre, Carlos; Gomes, Mario R.; A. A. M.Kuijk
Th.s paper discusses the design of a graphics board with parallel architecture based on Transputers and a resolution of 1024 x 1024 x 8 [VIN88], namely: Ihe processing unit (il plays the role of a display processor), the organization of the frame buffer and the video outpul hardware which includes the video controller and a RAMDAC (lookup-table + DACs).
A Massively Parallel Approach for the Design of a Raytracing Oriented Architecture
(The Eurographics Association, 1988) Muntean, T.; Waille, Ph.; A. A. M.Kuijk
Solving time critical problems requires a computing power of an order of magnitude greater than todays available conventional computers. The use of massively parallel architectures appears to be an attractive and effective way towards the required performances. The ray tracing technique is known as the best synthesis method for the construction of realistic images but also as the most time consuming. Computation time of several hours per image on a conventional mainframe is usual. Fortunately, this technique exhibits a huge amount of potential parallelism and therefore massively parallel architectures fit well and straightforwardly. This paper presents an efficient implementation of the ray tracing algorithm on a dedicated network of transputers. The INMOS's transputers are a family of monochip processors specially designed for parallel, asynchronous architectures without shared memory.
Point-driven Generation of Images from a Hierarchical Data Structure
(The Eurographics Association, 1988) Jong, Dirk de; Siobbe, Paul van; Splunter, Marinus van; A. A. M.Kuijk
In this paper, a system IS described which renders an image from a hierarchical data structure in a point-driven way. The data structure allows dynamic color mapping and arbitrary affine transformat·ons of objects with respect to their parent coordinate system. The point driven method allows for easy VLSI implementation, efficient use oj memory and exploitation of parallelism.
Combining Z-buffer Engines for Higher-Speed Rendering
(The Eurographics Association, 1988) Molnar, Steven; A. A. M.Kuijk
Described IS a hardware architecture for combining the outputs of a number of z-buffer rendering engines to achieve higher performance than is possible with a single renderer. It allows a combination of renderers to achieve the same pllce!performance ratio as the individual renderers that compose it. and can be extended to create systems with arbitrarily high periormance.The desCribed architecture is based on a fusion of scan-line rendering and the conventional z-buffer algorithm. The frame buffers of several z-buffer engines are modified to scan out z-values as well as color values. Multiplexing devices combine the z/color streams from each pair of frame-buffers. These z/color streams are then combined by further multiplexers, creating a binary tree that funnels the z/color information from the many conventional frame buffers Into a single z/color stream. The color stream is then used to dnve a standard display device.The proposed architecture allows rendering rates of millions and even tens of millions of polygons per second. The basic architecture can be extended with additional hardware to perform antialiasing and texture-mapping.
A VLSI Architecture for Image Composition
(The Eurographics Association, 1988) Shaw, Christopher D.; Green, Mark; Schaeffer, Jonathan; A. A. M.Kuijk
This paper describes a new parallel architecture for performing high-speed raster graphics. A central host broadcasts graphical objects to a number of identical graphics processors. Each graphics processor produces a raster depicting its graphical object on a transparent black background, and passes the raster to a leaf of a tree of VLSI processors called Compositors. Each Compositor combines a pair of rasters, performing anti-aliased hidden surface removal, and passes the composed raster to the next level of the tree. Appearing at the root of the tree is the final raster containing all objects at the correct depth with hidden surfaces removed. This paper gives an outline of the algorithm by Duff that the Compositor Will implement The algorithm proves to be too complex for our implementation technology, so a modification of Duff's algorithm is introduced. The high-level design of the dataflow part of the VLSI chip which implements this modified algorithm is then presented, followed by performance simulations and conclusion.
Content-Addressable Memories for Quadtree-8ased Images
(The Eurographics Association, 1988) Oldfield, J.V.; Williams, R.D.; Wiseman, N.E.; Brûlé, M.R.; A. A. M.Kuijk
Quadtrees are attractive for storing and processing mages with area coherence, but performance has been limited by software overheads. A Content-Addressable Memory (CAM) with ternary storage allows single-cycle searches by pixel coordinate, quadrant or rectangle. To use thiS feature effectively the authors have reviewed a range of quadtree processing functions relevant to computer graphics and Image processing, and some new algorithms have been discovere. The proposed VLSI chip has microcoded logic on each row, as well as its CAM cells. This architecture has been simulated in fine detail with the aid of the Connection Machine as well as by much slower, conventional computers. The combination of quadtrees and CAMs offers significant improvement in performance for display systems and image processing.
Hardware Support for the Display and Manipulation of Binary Voxel Models
(The Eurographics Association, 1988) Jense, G.J.; Huijsmans, D.P.; A. A. M.Kuijk
We describe some of our experiences with the implementation of a 3D reconstruction system for the visualization of the shapes and structural development of biological objects. We use a binary voxel model as volumetric representation of the reconstructed objects.The manipulation and display of volumetric representations involve the processing of huge amounts of data, making hardware support a virtual necessity. Instead of attempting to design special purpose hardware, we decided to try and exploit readily available image processing hardware.We use one of the available frame buffers for storage and direct display of the bi nary voxel data set. The other frame buffer holds either a surface normal view, a depth-shaded pre-image or the binary voxel data set of a secondary object. Altering the light direction or shading function IS performed by manipulating the hardware output lookup tables. An additional frame processor IS employed for running various filter operators over pre-images, computing bitwise logical functions on two binary voxel data sets and for pan and zoom operations.
An Integrated Highly Parallel Architecture for Image Reconstruction
(The Eurographics Association, 1988) Lattard, Didier; Mazare, Guy; A. A. M.Kuijk
The large amount of information and computations is a critical problem in image processing. In this paper we show a highly oarallel method to do image reconstruction which performs at real-time, using an asynchronous cellular array. The highly parallel architecture we propose is novel, its main characteristic is the message communication mechanism based upon message routing and mailbox principles.After introducing the image reconstruction problem, we present the main reconstructJon techniques and the sequential algorithms. We explain how to process these algorithms on a network. We describe this new integrated parallel architecture, its originalities and the system performing the whole reconstruction. We present the efficiency of this parallel Image reconstruction method and the performance of the network.
A Distributed Data Model for Raytracing
(The Eurographics Association, 1988) Skyttä, Jorma; Takala, Tapio; A. A. M.Kuijk
Ray tracing is a superior method for producing realistic images. It can take into account all natural phenomena covered by classical ray optics in image formation, and that without any extra modeling effort. The main disadvantage is its high cost in terms of computer time. Production of ray traced images of reasonably complex scenes takes long in real time with a moderate general purpose computer [Whi80).The basic idea of ray tracing is the brute force algorithm for simulating the path of a ray of light in the whole model space. As no global information of the model is used to anticipate the interactions of the ray with model elements, every ray must be tested against every object and most of the processing time is consumed to ray-object intersection calculation. At each intersection found the ray is divided into reflected and refracted components and into a ray directed to each light source to produce shadows. Higher quality images need more pixels to be calculated and the number of elements in a scene grows linearly with model complexity, leading to steep increase of the computational complexity of the whole problem.
The voxblt Engine: A Voxel Frame Buffer Processor
(The Eurographics Association, 1988) Kaufman, Arie; A. A. M.Kuijk
The voxblt Engine (vE) is a 3D frame-buffer processor which manipulates and processes ''3~ bitmaps"" (voxel maps) stored in a cubic frame buffer of voxels. The vE is the 3D counterpart of the 20 frame buffer processor, which is an extended version of the 20 bitbl/ and RasterOps engines.The primitives of the vE are subcubes of the cubic frame buffer and are of three kinds: rooms (3D windows), jacks (3D cursors), and figurines (3D ,cons). In addition to manipUlating these primitives, the vE also serves as a monitor for interaction, as an interfaoe for 3D input devices, and as a channel for inputling into the cubic frame buffer 3D voxel images from either 3D scanners or a voxel image database. The vE has been developed as part of the CUBE system, In which it operates as an Independent processor executing its own commands stored in a 3D frame-buffer display list. A room manager, which is the 3D counterpart of the 20 Window manager, has been implemented on top cf the vE
A VLSI Design Strategy for Graphics
(The Eurographics Association, 1988) Nimmo, AD.; Lister, P.F.; Grimsdale, R.L.; A. A. M.Kuijk
The tools available for ASIC design now offer the features and functionality necessary to permit ideas to be realised in silicon In a relatively short period of lime, This paper introduces work undertaken at Sussex University intended 10 lead to a more complete VLSI Design Strategy. Using ECAD packages provided by Mentor Graphics. In particular. it focuses on the use of Behavioural simulation tools and includes a worked example.
"A Display Controller for an Object-levelFrame Store System"
(The Eurographics Association, 1988) Jayasinghe, JAK.S.; Kuijk, A.A.M.; Spaanenburg, L.; A. A. M.Kuijk
In [3] and [1] a new architecture for a Computer Image Generating (CIG) system designed to have optimal interaction support for realistic 3D graphics has been presented. There it was stated that from an interaction paint of view there iS no need to have access to an image representation as low as the pixel level. This and the fact that the performance and resolution to a major extend has been limited by the pixe update speed enforced by memory technologies. led us to the conclusion that it should be investigated whether a CRT display could be refreshed from an object-level representation of the frame instead of the conventional pixel-level frame store. In thiS paper we present as a result of thiS study an architecture of a (multi-processor) Display Controller that is capable to directly refresh a raster display from such an Object-level frame representation.

Browse

Browsing EGGH88: Eurographics Workshop on Graphics Hardware 1988 by Issue Date

Results Per Page

Sort Options