EGGH93: Eurographics Workshop on Graphics Hardware 1993

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https://diglib7.eg.org/handle/10.2312/342

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An Architecture for Ray - Bezier Patch Intersection
(The Eurographics Association, 1993) Vijt, P De; Claesen, L; Man, H De; P. F. Lister and R. L. Grimsdale
A new fast ray - patch intersection algorithm is presented. The algorithm correctly handles all ray - patch intersections. A number of parametersare derived from a numerical analysis of the algorithm and the datapad is re synthesized for higher accuracy. A global architecture for anASIC for intersecting a ray with a bezier patch is presented. It is shownthat a cache combined with pre pads can reduce the required memory considerablewith an extremely small performance penalty. Attention will bepaid to the scheduling and control problem. Several high level optimizationsare presented that make efficient scheduling possible and decreasethe calculation time considerably.
CUBICORT: A Hardware Simulation of a Multicolumn Model for 3D Image Analysis, Understanding and Compression for Digital TV, HDTV and Multimedia
(The Eurographics Association, 1993) Leray, P; Burnod, Y; P. F. Lister and R. L. Grimsdale
We describe here simulation elements and results of a new kind of 3D Vision Machine. for pre-processing in 3D Object & movement analysis using the biological concept of the Cortical Column Paradigm in the primary visual area. The target machine is primarily dedicated to imagecompression for Telecommunication of TV, HDTV. and 3D TV. but can also be used for automatic modelling, digitizing, robotics or medical applications.
Designing a half toning coprocessor
(The Eurographics Association, 1993) Kugler, A; Hersch, R D; P. F. Lister and R. L. Grimsdale
Halftoning is a fairly slow process when executedby software on conventional processors. To speed uphalf toning, a half toning algorithm has been developed andintegrated into a dedicated hardware architecture. Thispaper describes the implementation of the architecturewith a XILINX Field Programmable Gate Array (FPGA)and compares its performances with results obtained by asoftware implementation. A discussion on how to improvethe present architecture concludes the paper.
A Difference Engine for Image Reconstruction
(The Eurographics Association, 1993) Blake, EH; Kuijk, AAM; P. F. Lister and R. L. Grimsdale
A diffetence engine is described that is designed to be used as low level component of a raster graphicsarchitecture. The speed of the system (11 ns per operation) is achieved by the use of custom VLSI componentsfor the most primitive operations. This permits the video rate reconstruction of images and other signalscompressed by encoding them on various polynomial bases. The paper describes a feasibility study for its usefor image reconstruction. The study shows that the system can be applied to the decompression of spline wavelet encoded images.
Direct Visualization of Quadrics
(The Eurographics Association, 1993) Laporte, H; Nyiri, E; Froumentin, M; Chaillou, C; P. F. Lister and R. L. Grimsdale
Today, most of the powerful graphic systems are based on 3D-triangle display methods.However, this approach generates well-known problems, like the low quality ofcontours and shading, and the necessity to have large amounts of primitives to displaycomplex scenes. A way to solve these problems is to use higher level primitives,among which a very interesting one is the quadric surface. We study here directvisualization of quadric surfaces (quadrics for short) .Although we study all the rendering process, we focus on the scan conversion stage.First, we present mathematical and modeling backgrounds where we show that aquadric surface can easily be rendered in scan-line. Then we give the general algorithmand details about the difficult part, i.e. the bounding plane algorithm. A functionaldescription of a scan converting processor is proposed, using a modular approach.In the last part, we give a hardware implementation of each module and the wholeprocessor. We also do an estimation of the silicon cost. The conclusion is that ourquadric patch scan converter can actually be realized.
Hemispherical Projection for Progressive Radiosity Calculation on Massively Parallel Architectures
(The Eurographics Association, 1993) Renaud, C; Bricout, F; Lepretre, E; P. F. Lister and R. L. Grimsdale
This paper describes a massively parallel implementation of the progressive radiosityalgorithm. Our algorithm is based on an hemispherical projection approach, which provides an accurate from factor approximation. As the projection plane is mapped onto a processor mesh, we propose different techniques decreasing computation timeby reducing as much as possible processor inactivity. This approach successfully handles large sets of form factor sampling elements.
A Parallel Accelerator for Generating Virtual Studio Sets
(The Eurographics Association, 1993) Sahiner, A V; Lefloch, P; Nimmo, A; Paker, Y; P. F. Lister and R. L. Grimsdale
Recent developments in digital video techniques and the use of computers in video andtelevision production provide new opportunities for programmes. Key technologies which embrace these developments are advanced computer graphics techniques for photorealistic rendering, image analysis and animation. Parallel processing providesthe potential for practical utilization of these techniques. We describe current researchin Electronic Set Design using high performance graphics workstations and a new parallel processing platform, for generating virtual studio sets.
Parallel Fixed Point Digital Differential Analyzer
(The Eurographics Association, 1993) Molla, RP; Quiros, R; Lluch, J; Vivo, R; P. F. Lister and R. L. Grimsdale
Two main serial algorithms to scan convert straight lines have beenproposed: Bresenham and Digital Differential AnalyzeLThe Bresenham algorithm has became a standard because of integer arithmetic. Many theoretical solutions have been proposed to parallelize Bresenham algorithm but its implementation is difficult. So most parallelizations take advantage of repeated patterns, massive parallel computers and so on. Sequential Digital Differential Analyzer shows better peformance than Bresenham if fixed pointarithmetic is used. This algorithm can be pipe lined and parallelized. It is easily hardware implemented and scalable. Hardware cost is linear with speedup. Utilization is nearly 100% and hardware waste is low.
Real-Time Architecture for High Resolution Volume Visualization
(The Eurographics Association, 1993) Pfister, H; Kaufman, A; P. F. Lister and R. L. Grimsdale
This paper describes a high-performance &pecial-purpose system, the Cube-3 machine, fordisplaying and manipulating high-resolution volumetric datasets in real-time. Cube-3 will allowscientists, engineers, and biomedical researchers to interactively visualize and investigate theirstatic high-resolution sampled, simulated, or computed volumetric dataset. Furthermore, onceacquisition devices or mechanisms are capable of acquiring a complete high-resolution dynamicdataset in real-time, Cube-S, tightly coupled with them, will be capable of delivering real-time 4D(spatial-temporal) volume visualization, a task currently not possible with present technologies.
The Role of Power Dissipation and Locality of Reference in the Specification of High Performance Graphics Algorithms
(The Eurographics Association, 1993) Smit, J.; Bentum, M.; Samsom, M.; P. F. Lister and R. L. Grimsdale
The amount of power dissipated by the implementation of an algorithm, for instance in the form of a dedicatedchip-set, is considered to be one of the most important constraints for the selection of a high performance graphicsalgorithm. This is due to the fact that the realization of computational capability within the reach of one Teraoperations per second is non-practical with general purpose CPU-chips. The case study of a high performancesurface visualization engine is used to introduce the reader with the aspect of power dissipation in relation tocomputational power. We introduce a low-power' parallel datapath' RISe processor, based on a highly efficientmapping of locality of reference in the algorithm onto silicon. A subsequent classification is made for varioushigh performance graphics algorithms.
VHDL Based Design of Graphics ASICs
(The Eurographics Association, 1993) White, M; Dunnett, G; Lister, P F; Grimsdale, R; P. F. Lister and R. L. Grimsdale
The design of graphics ASICs for geometry and rasterisation processing has traditionally involved the use of schematic design entry where by functional blocks are netlisted and instantiatedon the schematic. This methodology is fine at the top most hierarchical levels ofa design but becomes tedious and error prone at the lower gate levels. Often these designsare targetted at custom ASICs through the use of silicon compiler technology. Unfortunately,this is an expensive and risky approach to implementing these ASICs, particularlyfor University research laboratories where additional funding may not be available to covernon-recurring engineering costs, such as multiple mask runs, which may be needed due to design errors. This paper presents an alternative to these traditional approachs. A new approach, top down ASIC design with logic synthesis and optimisation targetting FPGAASICs, is presented . We demonstrate through some examples of our texturing and scanconversion hardware the benefits of this new approach.
A VLSI Design for Fast Vector Normalization
(The Eurographics Association, 1993) Knittel, G.; P. F. Lister and R. L. Grimsdale
The design of a vector normalizer is described. It is an integral part of our graphics subsystemfor scientific visualization, but will be of great use for speeding up any computer graphics architecture.In the actual design, the circuitry handles 3D-vectors with 33 bit two's complement components.The components of the normalized vectors are computed as 16 bit two's complementfixed-point numbers. Due to the overall pipeline architecture, the chip accepts one 3D-vectorand produces one normalized vector each clock.To normalize a 3D-vector, three square operations, two additions, one square root operationand three divisions must be performed. The target clock frequency is 50 MHz, by which theperformance of the chip rates at 450 MOPS.A single-chip VLSI implementation is currently in work, simulation results will be available bythe end of the third quarter '93. We use Mentor 8.2 tools on HP 700 workstations and Toshiba'sTC160G Gate Array technology.

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