EGGH89: Eurographics Workshop on Graphics Hardware 1989

Permanent URI for this collection

https://diglib.eg.org/handle/10.2312/346

Towards a Taxonomy for Display Processors

[meta data] [files:
003-036.pdf
]
Schneider, Bengt-Olaf

A Hardware Algorithm for Fast Realistic Image Synthesis

[meta data] [files:
037-060.pdf
]
Yilmaz, A. C.
; 
Hagestein, S.
; 
Deprettere, E.
; 
Dewilde, P.

PS: Polygon Streams A Distributed Architecture for Incremental Computation Applied to Graphics

[meta data] [files:
091-111.pdf
]
Gupta, Rajiv

The HERO Algorithm for Ray-Tracing Octrees

[meta data] [files:
061-073.pdf
]
Agate, Mark
; 
Grimsdale, Richard L.
; 
Lister, Paul F.

VLSI Architecture for Anti-Aliasing

[meta data] [files:
075-090.pdf
]
Romanova, Claudia
; 
Wagner, Ulrich

A Dedicated Graphics Processor SIGHT-2

[meta data] [files:
151-169.pdf
]
Yoshida, Masaharu
; 
Naruse, Tadashi
; 
Takahashi, Tokiichiro

Two-level Pipelining of Systolic Array Graphics Engines

[meta data] [files:
133-148.pdf
]
Jayasinghe, J. A. K. S.
; 
Herrmann, O. E.

A Generalised Parallel Architecture for Image Based Algorithms

[meta data] [files:
113-132.pdf
]
Vaudin., G. J.
; 
Nudd., G. R.
; 
Atherton, T. J.
; 
Clippingdale, S. C.
; 
Francis., N. D.
; 
Kerbyson., R.M. Howarth. D. J.
; 
Packwood, R. A.
; 
Walton, D.

A Real-Time Raster Scan Display for 3-D Graphics

[meta data] [files:
213-227.pdf
]
D.Jackèl,
; 
Günther, H.
; 
Herwig, B.
; 
Rüsseler, H.

A Virtual Memory System Organization for Bit-Mapped Graphics Displays

[meta data] [files:
199-212.pdf
]
Barkans, Anthony C.

Viewing and Rendering Processor for a Volume Visualization System

[meta data] [files:
171-178.pdf
]
Kaufman, A.
; 
Bakalash, R.
; 
Cohen, D.

Presentation of the Cubi9000: A Graphics System based on Inmos T800 Transputers

[meta data] [files:
179-198.pdf
]
Glemot, France

A Distributed Frame Buffer within a Window-Oriented High Performance Graphics System

[meta data] [files:
261-274.pdf
]
Haaker, Thomas
; 
Selzer, Harald
; 
Joseph, Hans

The Graphics Unit of the INTEL 180860

[meta data] [files:
229-247.pdf
]
Kursawe, Ulrich

A Chinese-Character and Graphics Workstation

[meta data] [files:
249-260.pdf
]
Jiaoying, Shi
; 
Jian/eng, Huang
; 
Liancai, Liu
; 
Jingyi, Hu

BibTeX (EGGH89: Eurographics Workshop on Graphics Hardware 1989)
@inproceedings{
:10.2312/EGGH/EGGH89/003-036,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Richard Grimsdale and Wolfgang Strasser
},
title = {{
Towards a Taxonomy for Display Processors}},

author = {
Schneider, Bengt-Olaf
},
year = {
1989},

publisher = {
The Eurographics Association},


ISSN = {1727-3471},
ISBN = {ISBN 3-540-53473-3},

DOI = {
/10.2312/EGGH/EGGH89/003-036}

}
@inproceedings{
:10.2312/EGGH/EGGH89/037-060,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Richard Grimsdale and Wolfgang Strasser
},
title = {{
A Hardware Algorithm for Fast Realistic Image Synthesis}},

author = {
Yilmaz, A. C.
 and 
Hagestein, S.
 and 
Deprettere, E.
 and 
Dewilde, P.
},
year = {
1989},

publisher = {
The Eurographics Association},


ISSN = {1727-3471},
ISBN = {ISBN 3-540-53473-3},

DOI = {
/10.2312/EGGH/EGGH89/037-060}

}
@inproceedings{
:10.2312/EGGH/EGGH89/091-111,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Richard Grimsdale and Wolfgang Strasser
},
title = {{
PS: Polygon Streams A Distributed Architecture for Incremental Computation Applied to Graphics}},

author = {
Gupta, Rajiv
},
year = {
1989},

publisher = {
The Eurographics Association},


ISSN = {1727-3471},
ISBN = {ISBN 3-540-53473-3},

DOI = {
/10.2312/EGGH/EGGH89/091-111}

}
@inproceedings{
:10.2312/EGGH/EGGH89/061-073,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Richard Grimsdale and Wolfgang Strasser
},
title = {{
The HERO Algorithm for Ray-Tracing Octrees}},

author = {
Agate, Mark
 and 
Grimsdale, Richard L.
 and 
Lister, Paul F.
},
year = {
1989},

publisher = {
The Eurographics Association},


ISSN = {1727-3471},
ISBN = {ISBN 3-540-53473-3},

DOI = {
/10.2312/EGGH/EGGH89/061-073}

}
@inproceedings{
:10.2312/EGGH/EGGH89/075-090,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Richard Grimsdale and Wolfgang Strasser
},
title = {{
VLSI Architecture for Anti-Aliasing}},

author = {
Romanova, Claudia
 and 
Wagner, Ulrich
},
year = {
1989},

publisher = {
The Eurographics Association},


ISSN = {1727-3471},
ISBN = {ISBN 3-540-53473-3},

DOI = {
/10.2312/EGGH/EGGH89/075-090}

}
@inproceedings{
:10.2312/EGGH/EGGH89/151-169,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Richard Grimsdale and Wolfgang Strasser
},
title = {{
A Dedicated Graphics Processor SIGHT-2}},

author = {
Yoshida, Masaharu
 and 
Naruse, Tadashi
 and 
Takahashi, Tokiichiro
},
year = {
1989},

publisher = {
The Eurographics Association},


ISSN = {1727-3471},
ISBN = {ISBN 3-540-53473-3},

DOI = {
/10.2312/EGGH/EGGH89/151-169}

}
@inproceedings{
:10.2312/EGGH/EGGH89/133-148,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Richard Grimsdale and Wolfgang Strasser
},
title = {{
Two-level Pipelining of Systolic Array Graphics Engines}},

author = {
Jayasinghe, J. A. K. S.
 and 
Herrmann, O. E.
},
year = {
1989},

publisher = {
The Eurographics Association},


ISSN = {1727-3471},
ISBN = {ISBN 3-540-53473-3},

DOI = {
/10.2312/EGGH/EGGH89/133-148}

}
@inproceedings{
:10.2312/EGGH/EGGH89/113-132,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Richard Grimsdale and Wolfgang Strasser
},
title = {{
A Generalised Parallel Architecture for Image Based Algorithms}},

author = {
Vaudin., G. J.
 and 
Nudd., G. R.
 and 
Atherton, T. J.
 and 
Clippingdale, S. C.
 and 
Francis., N. D.
 and 
Kerbyson., R.M. Howarth. D. J.
 and 
Packwood, R. A.
 and 
Walton, D.
},
year = {
1989},

publisher = {
The Eurographics Association},


ISSN = {1727-3471},
ISBN = {ISBN 3-540-53473-3},

DOI = {
/10.2312/EGGH/EGGH89/113-132}

}
@inproceedings{
:10.2312/EGGH/EGGH89/213-227,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Richard Grimsdale and Wolfgang Strasser
},
title = {{
A Real-Time Raster Scan Display for 3-D Graphics}},

author = {
D.Jackèl,
 and 
Günther, H.
 and 
Herwig, B.
 and 
Rüsseler, H.
},
year = {
1989},

publisher = {
The Eurographics Association},


ISSN = {1727-3471},
ISBN = {ISBN 3-540-53473-3},

DOI = {
/10.2312/EGGH/EGGH89/213-227}

}
@inproceedings{
:10.2312/EGGH/EGGH89/199-212,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Richard Grimsdale and Wolfgang Strasser
},
title = {{
A Virtual Memory System Organization for Bit-Mapped Graphics Displays}},

author = {
Barkans, Anthony C.
},
year = {
1989},

publisher = {
The Eurographics Association},


ISSN = {1727-3471},
ISBN = {ISBN 3-540-53473-3},

DOI = {
/10.2312/EGGH/EGGH89/199-212}

}
@inproceedings{
:10.2312/EGGH/EGGH89/171-178,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Richard Grimsdale and Wolfgang Strasser
},
title = {{
Viewing and Rendering Processor for a Volume Visualization System}},

author = {
Kaufman, A.
 and 
Bakalash, R.
 and 
Cohen, D.
},
year = {
1989},

publisher = {
The Eurographics Association},


ISSN = {1727-3471},
ISBN = {ISBN 3-540-53473-3},

DOI = {
/10.2312/EGGH/EGGH89/171-178}

}
@inproceedings{
:10.2312/EGGH/EGGH89/179-198,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Richard Grimsdale and Wolfgang Strasser
},
title = {{
Presentation of the Cubi9000: A Graphics System based on Inmos T800 Transputers}},

author = {
Glemot, France
},
year = {
1989},

publisher = {
The Eurographics Association},


ISSN = {1727-3471},
ISBN = {ISBN 3-540-53473-3},

DOI = {
/10.2312/EGGH/EGGH89/179-198}

}
@inproceedings{
:10.2312/EGGH/EGGH89/261-274,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Richard Grimsdale and Wolfgang Strasser
},
title = {{
A Distributed Frame Buffer within a Window-Oriented High Performance Graphics System}},

author = {
Haaker, Thomas
 and 
Selzer, Harald
 and 
Joseph, Hans
},
year = {
1989},

publisher = {
The Eurographics Association},


ISSN = {1727-3471},
ISBN = {ISBN 3-540-53473-3},

DOI = {
/10.2312/EGGH/EGGH89/261-274}

}
@inproceedings{
:10.2312/EGGH/EGGH89/229-247,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Richard Grimsdale and Wolfgang Strasser
},
title = {{
The Graphics Unit of the INTEL 180860}},

author = {
Kursawe, Ulrich
},
year = {
1989},

publisher = {
The Eurographics Association},


ISSN = {1727-3471},
ISBN = {ISBN 3-540-53473-3},

DOI = {
/10.2312/EGGH/EGGH89/229-247}

}
@inproceedings{
:10.2312/EGGH/EGGH89/249-260,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Richard Grimsdale and Wolfgang Strasser
},
title = {{
A Chinese-Character and Graphics Workstation}},

author = {
Jiaoying, Shi
 and 
Jian/eng, Huang
 and 
Liancai, Liu
 and 
Jingyi, Hu
},
year = {
1989},

publisher = {
The Eurographics Association},


ISSN = {1727-3471},
ISBN = {ISBN 3-540-53473-3},

DOI = {
/10.2312/EGGH/EGGH89/249-260}

}

Browse

Recent Submissions

Now showing 1 - 15 of 15
  • Thumbnail Image
    Item
    Towards a Taxonomy for Display Processors
    (The Eurographics Association, 1989) Schneider, Bengt-Olaf; Richard Grimsdale and Wolfgang Strasser
    Image generation for raster displays proceeds in two main steps: geometry processing and pixel processing. The snbsystem performing the pixel processing is called display processor.In the paper a model for the displa.y processor is developed that takes into account both function and timing properties. The model identifies scan conversion, hidden surface removal, shading and anti-aliasing as tile key functions of the display processor. The timing model is expressed in an inequation being fundamental for all display processor architectures.On the basis of that model a taxonomy is presented which classifies display processors according to four main criteria: function, partitioning, a.rchitecture and performance.The taxonomy is applied to five real display processors: Pixel-planes, SLAM, PROOF, the Ray-Casting Machine and the Structured Frame Store System.Investigation of existing display processor architectures on the basis of the devel oped taxonomy revealed a potential new architecture. This architecture partitions the image generation process ill image space and employs a. tree topology.
  • Thumbnail Image
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    A Hardware Algorithm for Fast Realistic Image Synthesis
    (The Eurographics Association, 1989) Yilmaz, A. C.; Hagestein, S.; Deprettere, E.; Dewilde, P.; Richard Grimsdale and Wolfgang Strasser
    A VLSI oriented algorithm, for the implementation of a generalized two-pass radiosity method is presented. The method allows any reflection behavior, varying from purely diffuse to perfect mirroring. Moreover, objects may be defined in terms of curved (Bezier) surfaces. All computations in the pre- and postprocess are similar and ray-tracing based, consequently a single architecture can be devised for both passes. This architecture, when built on ray-rotating and ray-tracing pipelined processors such as Cordics, results in a very high throughput VLSI implementation o f the proposed generalized two-pass procedure.
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    PS: Polygon Streams A Distributed Architecture for Incremental Computation Applied to Graphics
    (The Eurographics Association, 1989) Gupta, Rajiv; Richard Grimsdale and Wolfgang Strasser
    Polygon Streams is a distributed system with multiple processors a.nd strictly local communication. A unique custom VLSI chip that constitutes an independent processing module forms a stage of the PS pipeline. The number of these modules in PS is a variable that is determined by the application. PS features a modular ar­ chitecture, multi-ported on-chip memory, bit-serial arithmetic, and a pipeline whose computation can be dynamically configured. The PS design closely subscribes to the system characteristics favored by VLSI.The task of scan conversion for rendering computer graphics images on raster scan displays is very intensive in computation and pixel information access. It is very coherent and suitable, however, for forward difference algorithms. The discrete and regular layout of the raster display, in conjunction with the largely local effect of a pixel on an image, make rendering amenable to parallel architectures with localized memory and communication. These are precisely the attributes favored by VLSI and typical of PS.A modification of the Digital Differential Analyzer (DDA) is implemented to Gouraud Shade and depth buffer convex polygons at high speeds. The scan conver­ sion task is distributed over the processors to efficiently subdivide the image space and maximize concurrency of processor operation.A study of the tradeoffs and architectural choices of the PS reveal the merits and deficits ofthe PS approach in comparison with Pixel-Planes, SLAMs, Super-Buffers, and SAGE.
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    The HERO Algorithm for Ray-Tracing Octrees
    (The Eurographics Association, 1989) Agate, Mark; Grimsdale, Richard L.; Lister, Paul F.; Richard Grimsdale and Wolfgang Strasser
    An algorithm is presented for rapid traversal of octree data structures, in order to enhance the speed of ray tracing for scenes of high complexity. At each level of the octree, the algorithm generates the addresses of child voxels in the order they are penetrated by the ray. This requires only a few arithmetic operations and simple logical operations. A depth-first search of the tree is used to yield the first terminal voxel hit by the ray, thus hidden objects are not processed. The algorithm is designed specifically for implementation as HERO: A Hardware Enhancer for Ray-tracing Octrees.
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    VLSI Architecture for Anti-Aliasing
    (The Eurographics Association, 1989) Romanova, Claudia; Wagner, Ulrich; Richard Grimsdale and Wolfgang Strasser
    Computer-synthesized images exhibit the typical artifacts of raster displays, called alias­ ing, rastering, staircasing or the "jaggies". Display of an image on a raster CRT requires the sampling the two dimensional image signal I( x, y) to obtain a pixel-based description of intensity. Unfortinately, this sampling process treates the pixel as a mathematical point and the point sampling of an unfiltered object is never correct at any resolution. Aliasing effects (spatial and temporal) are due to undersampling of the image signal. Spatial aliasing occurs when images contain frequencies greater than one half the spa­ tial sampling frequency. Lines that should be straight appear jagged, very small objects may not be visible, portions of long thin objects may disappear.
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    A Dedicated Graphics Processor SIGHT-2
    (The Eurographics Association, 1989) Yoshida, Masaharu; Naruse, Tadashi; Takahashi, Tokiichiro; Richard Grimsdale and Wolfgang Strasser
    SIGHT-2 is a multiprocessor system that is intended to efficiently execute the ray tracing algorithm. To achieve high efficiency, three kinds of parallel execution mechanisms; (i) a multiprocessor configuration, (ii) a parallel execution of three dimensional vector operations, and (iii) functionally distributed parallel processing are introduced. Owing to the latter two techniques, each processing element (PE) has the ability to execute the standard ray tracing algorithm 10 times faster than a VAX11/780 with a floating point accelerator. In the present con­ figuration, SIGHT-2 utilizes 16 PEs, which results in a peak power of 66.72 MFLOPS / 133.28 MIPS. During ray tracing, the efficiency of each PE is over 99% under static load balancing.In this paper, SIGHT-2 system architecture, its PE configuration, and VLSIs design are discussed. The system performance is also discussed.
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    Two-level Pipelining of Systolic Array Graphics Engines
    (The Eurographics Association, 1989) Jayasinghe, J. A. K. S.; Herrmann, O. E.; Richard Grimsdale and Wolfgang Strasser
    In a systolic array, the maximum operating speed is determined by the most complex operation performed. In a systolic army graphics engine, capable of generating high quality images, one has to perform complex operations at a very high speed. We propose to use pipelined functional units in systolic army graphics engines as they can perform complex operations at high speeds. Due to time-varying discontinuities of operations performed by systolic army graphics engines, introduction of pipelined functional units is a complex problem. In this paper we present a methodology which solves this problem by a graph­ theoretic approach. Furthermore, we characterize the architectures which can be improved by pipelined functional units. Categories and Subject Descriptors: B.7.1 [Integrated Circuits}: Types and Design Styles VLSI C.l.1 [Single Data Stream Architectures}: Pipeline Processors C.S [Special-purpose and Application Based Systems}: Real-time Systems 1.3.1 [Computer Graphics]: Hardware Architecture - Raster Display Devices 1.3.7 [Computer Graphics]: Three-dimensional Graphics and Realism Color, Shading, Shadowing and Texture
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    A Generalised Parallel Architecture for Image Based Algorithms
    (The Eurographics Association, 1989) Vaudin., G. J.; Nudd., G. R.; Atherton, T. J.; Clippingdale, S. C.; Francis., N. D.; Kerbyson., R.M. Howarth. D. J.; Packwood, R. A.; Walton, D.; Richard Grimsdale and Wolfgang Strasser
    Real time image generation and image understanding require levels of computing power, that are beyond that available from conventional sequential machines. Current commercially available systems aimed at this area make use of special purpose hardware to achieve the necessary throughput, but these systems can only achieve their performance for a restricted set of algorithms that are implemented in the hardware. A programmable general purpose parallel machine offers the possibility to achieve the required performance without restricting the choice of algorithm.Unfortunately it is by no means clear which parallel architecture should be used. Many general purpose parallel architectures have been proposed but none has proved universally applicable, their problem being that their performance tends to be highly dependent on the algorithms that are being used, and it is therefore difficult to claim any of them are truly general purpose. However parallel machines can still be highly effective in specific problem areas where the class of algorithm is known.Our aim has been to design a parallel machine that is optimised for image based algorithms in both graphics and image understanding. The architecture is not limited to a specific set of algorithms, but is instead optimised towards a class of algorithms which we believe are representative of image based algorithms. This has not been a paper study, but has resulted in us implementing such an architecture. We have achieved this by making use of industry standard components and integrating them into a system level architectural design. Also we have where possible used industry standard programming languages to program our machine.
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    A Real-Time Raster Scan Display for 3-D Graphics
    (The Eurographics Association, 1989) D.Jackèl,; Günther, H.; Herwig, B.; Rüsseler, H.; Richard Grimsdale and Wolfgang Strasser
    This paper describes the architecture of a raster scan display for real-time visualisation of shaded polygons. A performance of 15-106 Phong shaded pixels per second is a primary goal of a pipelined rendering processor. The performance of the geometry processor, which is responsible for the geometrical transformations, the 3-d clipping and the perspective projection, will exceed 100,000 triangle shaped polygons.Following a survey of the entire 3-d real-time system, we will describe architectural details of the rendering processor. Finally, the main features enabled by the architecture are highlighted.
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    A Virtual Memory System Organization for Bit-Mapped Graphics Displays
    (The Eurographics Association, 1989) Barkans, Anthony C.; Richard Grimsdale and Wolfgang Strasser
    Described is a display sub-system, designed for support of a very high speed rendering engine. It provides high-performance graphics to an enVironment that consists of a hierarchy of resizable windows. The concept of virtual memory has been applied with the organization of the virtual to physical address spaces having a unique mapping that fits the organization of a bit-mapped graphics memory display.
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    Viewing and Rendering Processor for a Volume Visualization System
    (The Eurographics Association, 1989) Kaufman, A.; Bakalash, R.; Cohen, D.; Richard Grimsdale and Wolfgang Strasser
    The architecture and the hardware realization of the 3D Viewing and Rendering Pro­ cessor is presented. This processor is a component of the Cube architecture, developed primarily for volume visualiza.tion. The processor generates 2D shaded orthographic, parallel, and perspective projections of the volumetric image of n 3 vox­ els in O(n210gn) time. This performance is attributed to a unique skewed memory organization, a special ray projection bus, an extended viewing architecture, and a new congradient shading technique. A reduced-resolution prototype has been real­ ized in hardware using printed circuit board technology and has been running in true real time. Currently, a VLSI version of the prototype is being tested.
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    Presentation of the Cubi9000: A Graphics System based on Inmos T800 Transputers
    (The Eurographics Association, 1989) Glemot, France; Richard Grimsdale and Wolfgang Strasser
    The Cubi9000 family includes a range of products from the 3D graphics terminal up to the 3D graphics workstation. The Cubi9000 when configured as a 3D graphics terminal connects to a host computer via a parallel interface from Digital Equipment Corporation. The Cubi9000 configured as workstation includes a UNIX2 based mini-computer with a 32 bit microprocessor, mass memory, device handlers (mouse, tablets, encoders) and communication drivers to external systems.
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    A Distributed Frame Buffer within a Window-Oriented High Performance Graphics System
    (The Eurographics Association, 1989) Haaker, Thomas; Selzer, Harald; Joseph, Hans; Richard Grimsdale and Wolfgang Strasser
    Today's workstation users demand high computational performance combined with powerful graphics and a comfortable window system. Existing and forthcoming standards like OKS-3D, PHIOS/PHIGS+, X Window System, and PEX have to be supported optimally.This paper presents the architecture of a graphics engine designed to meet the above requirements. Utilizing a distributed frame buffer pixel access with a high bandwidth is achieved. Several functions of a window management system like clipping at arbitrarily shaped window boundaries, fast copying of windows and performing Bit-Block-Transfer operations (BitBIT) are performed by hardware. Finally, a homogeneous and load-adaptive multiprocessor configuration for geometry and rendering calculation is described.
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    The Graphics Unit of the INTEL 180860
    (The Eurographics Association, 1989) Kursawe, Ulrich; Richard Grimsdale and Wolfgang Strasser
    The Intel 180860 is a very powerful RISe processor, designed for applications that require a large amount of floating point and integer calculations. Additionally it supports graphics applications with a Graphics hardware unit. The aim of this article is to investigate, for which application this unit is useful and whether the results obtained by the help of this unit are better as with standard e or assembly implementations of the same algorithm.
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    A Chinese-Character and Graphics Workstation
    (The Eurographics Association, 1989) Jiaoying, Shi; Jian/eng, Huang; Liancai, Liu; Jingyi, Hu; Richard Grimsdale and Wolfgang Strasser
    This paper introduces the design approaches of a Chinese-character and graphics workstation OOS-80OO which has been developed at the Computer Graphics Research Laboratory, Department of Computer Science and Engineering, Zhejiang University. The specifications, architecture, Chinese-character processing environment and working modes of the workstation are described. Especially the 110 interface with the host computer. the processor unit, the graphics g-eneration and display unit, Chinese­ character operating system and some main input modes of Chinese-character codes are introduced in detail.