Compiling to a VLIW Fragment Pipeline

Mark, William R.; Proudfoot, Kekoa

Compiling to a VLIW Fragment Pipeline

Date

2001

Authors

Mark, William R.
Proudfoot, Kekoa

Publisher

The Eurographics Association

Abstract

The latest generation of graphics hardware supports fully programmable vertex and pixel/fragment operations, but programming this hardware at a low level is difficult and time consuming. To address this problem, we have developed a complete real-time procedural shading system that compiles a high-level shading language to programmable vertex and fragment hardware, as described in a separate publication. In this paper, we describe in detail the algorithms used by this system to generate and optimize fragment code for NVIDIAs register combiner architecture and show that our compiler generates efficient code. The register combiner architecture has some similarities to WIW CPU architectures, so we compare our compilation algorithms to those described in the literature for VLIW CPU architectures. We also discuss some of the lessons we leamed from building and using this compiler that may be useful to the designers of future programmable graphics hardware.

        @inproceedings{:10.2312/EGGH/EGGH01/047-055
,
booktitle = {Eurographics/SIGGRAPH Graphics Hardware Workshop 2001
},
editor = {Kurt Akeley and Ulrich Neumann
},
title = {{Compiling to a VLIW Fragment Pipeline
}},
author = {Mark, William R. and 
Proudfoot, Kekoa
},
year = {2001
},
publisher = {The Eurographics Association
},
ISSN = {1727-3471
},
ISBN = {158113407X
},
DOI = {/10.2312/EGGH/EGGH01/047-055
}
}

URI

https://doi.org/10.2312/EGGH/EGGH01/047-055

Collections

EGGH01: SIGGRAPH/Eurographics Workshop on Graphics Hardware 2001

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