Eurographics Workshops and Symposia

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Looking at Workstation Architectures from the Viewpoint of Interaction
(The Eurographics Association, 1986) Krömker, Detlef; W. Strasser
Today's design of sophisticated graphics workstations may be characterized by the terms 3D-system, user driven, object-oriented user interfaceand multiple-windows system with the challenge to create high levelinterfaces for the application programmers. All these properties requirea great amount of computing power, especially if we look at 3D-systemswith high images quality. On the other hand it is well-known that speed,which means system response time, is the most important aspect of interactive systems. More than any other attributes, speed decides whether a new system or technique is acceptable or not. "Not only did the speed make the user happier, but productivity went up." /Brad-85/This will be the first point of discussion treated in this article followed bya preview of current architectures, a short analysis of interaction, anobservation of implementation techniques and finally pointing out a newhardware approach for the implementation of very fast interactive systems.
A Visual System for a Traffic Simulator
(The Eurographics Association, 1986) Möller, R.; W. Strasser
The prototype of a modular CGI-system for real time simulation in atraffic simulator will be presented. It will be shown, that withthe proposed configuration of a large asymmetric multiprocessorsystem, organized in different layers of homogenous partial, systems, and an overlayed pipeline - architecture the usage ofcommon hardware components is generally possible for the realizationof low cost solutions.
Display Architecture for VLSI -based Graphics Workstations
(The Eurographics Association, 1986) Hagen, P. J. W. ten; Kujik, A. A.M.; Trienekens, C. G.; W. Strasser
At present, two popular development areas in computer graphics are improvement ofinteraction behaviour and more realistic graphics.The architecture for a high quality interactive workstation proposed in this work isdesigned such that both demanding and in a sense competing needs can be served.Calculations for generating realistic full 3-D scenes with lighting, transparency,reflection, and refraction effects, are done on the workstation itself. Intermediateresults are stored to locally serve high level interaction mechanisms.
Towards a Z-Buffer and Ray-Tracing Multimode System based on Parallel Architecture and VLSI chips
(The Eurographics Association, 1986) P.Lemy,; W. Strasser
After the hidden surfaces algorithms for 3D rastergraphics, hardware design isthe main problem, for many applicat ions, such as : Audiovisual animat ions. CADCAM,and simulation.After a short description of our CUBI 7 system (a 3D real-time Z-buffer system),and its CRISTAL module which increases RAY-TRACING computations, we present ourhardware project based on :-Parallel architecture for RAY-TRACING, special effects ; This module is alsouseful for pre-processing the image : (rotations, clipping, perspective transform... ).-A or Z-BUFFER which will be designed on VLSI chips polygon filling will be alsodesigned with pipe-lined chips."
Developments in High Performance CGI Systems
(The Eurographics Association, 1986) Grimsdale, R L.; Lister, P. F.; W. Strasser
This contribution describes some work being undertaken in the design andimplementation of architectures for high performance Computer Image Generationfor a range of applications from workstations to flight simulator visual systems.The work to be described uses a model based on a polygon representation anduses a Geometry Processor sub-system, with a flexible architecture known asMAGIC. This system performs the transformation of the polygon from the 3-Drepresentation to the 2-D perspective projection to the viewing screenco-ordinates and also provides a clipping operation optional in 3-D or 2-D.Two different types of scan conversion system are described, the first the ZoneManagement Processor uses the coherence inherent in the polygon and thesecond system based on a Line Processor uses coherence with spans.
AVLSI Chip for Ray Tracing Bicubic Patches
(The Eurographics Association, 1986) Pulleyblank, R W.; Kapenga, J.; W. Strasser
A VLSI chip for ray tracing bicubic patches in Bezier form is explored. The purpose of the chip is to calculate the intersection point of a ray with the bicubic patch to a specified level of accuracy, returning the location of the intersection on the patch and on the ray. This is done by computing the intersection of the ray with a bounding volume of the patch and repeatedly subdividing the patch until the bounding volume of subpatches hit by the ray is smaller than the accuracy requirement. There are two operating modes, one in which only the nearest intersection is found and another in which all intersections are found. This algorithm correctly handles rays tangentially intersecting a planar patch and ray intersections at a silhouette edge of the patch. Estimates indicate that such a chip could be implemented in 2 micron NMOS and could compute patch/ray intersections at the rate of one every 15 microseconds for patches that are prescaled and specified to 12 bits fixed point for each of the x, y and z components. A version capable of handling 24 bit patches could compute patch/ray intersections at the rate of one every 140 microseconds. Images drawn using a software version of the algorithm are presented and discussed.
CSG Hidden Surface Algorithms for VLSI Hardware Systems
(The Eurographics Association, 1986) Jansen, Frederik W.; W. Strasser
Constructive Solid Geometry (CSG) is a solid modeling representation thatdefines objects ·as Boolean combinations of primitive solids. For thedisplay of such objects, both the visibility problem and the problem ofcombining the primitive solids into one composite object have to be solved.Recently, several CSG hidden surface algorithms have been published thatreduce these two problems to a combination of simple depth comparisons andlogical operations at the pixel level that can be performed in VLSI hardwaredisplay systems. An overview of these algorithms is given. Furthermore,a CSG depth-buffer algorithm is presented that combines these algorithms.
"Position Paper:Display Hardware for Boolean Expression Models"
(The Eurographics Association, 1986) Thomas, A. L.; W. Strasser
In any discussion of graphics hardware there appear to be two basic positions which can be adopted. The first is that of the technologist, who is primarily concerned with what it is possible to make and how to make it. The second is that of the system designer who is more interested in what it would be desirable to make. To be a designer it is necessary to have a view of the future ... or at least a view of a plausible future! This is only possible with a reasonably sound idea of what the technologists might be persuaded to provide. I suspect that most of the "images of the future" which have guided or moulded current proposals have been around for some time. In spite of this it is a good preliminary exercise to set out a brief statement of the main ideas Which lie behind current developments, before homing in on specific hardware proposals.
Utilization of VLSI for Creating an Active Data Base of 3-D Geometric Models
(The Eurographics Association, 1986) Skyttä, J.; Takala, T.; W. Strasser
Parallelism of geometric computation can be achieved by distributing the computation efforts according to essentially three different strategies, based on functional, spatial and structural division, respectively (Mantyla 1983). The conventional and already commercialized way to introduce parallel computation for viewing 3-D geometric models is employing functional parallelism as a pipeline for performing different sequential transformation phases of the 3-D viewing operation (Clark 1981). This approach limits the number of parallel activities to the number of separable functional computational modules. A second approach for parallelism is the division of the modeling space into separable volume elements, which can be processed independently using a suitable data structure like an octree(Kronlof 1985). The logical component structure of a model gives a third distribution strategy. Then each processor answers only to the computational needs of its assigned objects.
Towards a 3-D Graphics Workstation
(The Eurographics Association, 1986) Kaufmann, Arie; W. Strasser
A voxel-map based architecture which lays the foundations for a 3-D graphics workstation,called the CUBE Workstation, is presented. The architecture is centered around a largecubic frame-buffer of voxels, operated on by three processors: a 9-D Geometry Processorwhich scan-converts geometric objects into their voxel representation, a 9-D Frame-BufferProcessor which manipulates the voxel-based images and controls interaction, and a 9-DViewing Processor which projects the images on a 2-D monitor. Two other supportingprocessors, the 2-D Frame-Buffer Processor which manipulates the 2-D images and theColor Transform Processor which handles color transformations, are also introduced.
A Survey of Simulator Requirements
(The Eurographics Association, 1986) Joseph, H.; W. Strasser
Simulators have been developed to train pilots, sailors or car drivers withoutthe costs and risks of moving their real vehicles. To obtain high success intraining, the simulators have to provide a high level of realism. Therequirements of simulators and their CIG-system, especially the 'real time'requirement, result from this need for realism. 'Real time' means, the systemhas to react in less than 150 ms after the trainnee has made an input.
Partially Ordered Search Indices in the Organizationof a Fixed Hierarchy
(The Eurographics Association, 1987) Skyttä, Jorma; Takala, Tapio; Fons Kuijk and Wolfgang Strasser
"IntroductionThe mapping of even very advanced algorithms directly to hardware does not typically bring good results as these algorithms are originally designed for sequential processing. However, the power of the modern integration technology lies in its ability to produce high volumes of reasonably complex elements at moderate cost. For utilization of these possibilities the algorithms and data structures already developed must be redesigned for parallel computation."
Cellular Architectures and Algorithmsfor Image Synthesis
(The Eurographics Association, 1987) Meriaux, Michel; Fons Kuijk and Wolfgang Strasser
The aim of this paper is to provide some refiexions and partial results about cellular architectures for image synthesis and graphics. As some steps of image synthesis involve a long processing time, quite incompatible with interactivity, a natural solution consists in parallel processing. Though a lot of work has been done about cellular hardware, only a little exists about cellular graphic algorithms and hardware.
Ray Tracing Rational B-Spline Patches in VLSI
(The Eurographics Association, 1987) Schneider, Bengt-Olaf; Fons Kuijk and Wolfgang Strasser
Rational B-spline surfaces make it possible to merge the concepts of freeform surfaces and that of surfaces described by rational polynomials especially conic sections. For ray tracing it is crucial to determine the intersection between ray and object. Therefore an algorithm is developed that is suitable for a VLSI implementation. Some alternatives for the implementation of this algorithm are presented and discussed. The paper concludes with a discussion of some problems and possible further developments.
An O(log N) Parallel Time Exact Hidden-LineAlgorithm
(The Eurographics Association, 1987) Dévai, F.; Fons Kuijk and Wolfgang Strasser
"Parallel algorithms are given for the exact solution of the hidden-line problem. Most of the parallel algorithms proposed for visibility problems in the literature give approximate solutions. and thus cannot yield an upper bound on the complexity of the particular problem. The first algorithm proposed here is worth mentioning not only for its simplicity. but also from a practical point of view: a speed up of a factor P is achieved by using P processors. l"";;P"";;N. where N is the number of edges used to describe a polygonal scene. Additionally. the problem of aliasing inherent with approximation methods is avoided.The significance of the second algorithm, which is based on the first one, is mainly on the theoretical level: it is used to establish the parallel complexity of the hidden-line problem. The sequential complexity of this problem has recently been proved to be e(N2). and now we can prove that in the parallel case the problem is in the complexity class NC, Le., it can be solved in time polynomial in logN by using a number of processors polynomial in N, assuming any reasonable model of parallel computation. More particularly, an O(logN) parallel time solution is given which cannot be further improved even if arbitrarily many processors of a concurrent read, exclusive write parallel RAM model are available."
A Vector-like Architecture for Raster Graphics
(The Eurographics Association, 1987) Akman, Varol; Hagen, Paul ten; Kuijk, Fons; Fons Kuijk and Wolfgang Strasser
Raster graphics, while good at achieving realistic and cost-effective image generation, lacks useful (e.g. high-level) and fast (e.g. almost real-time) interaction facilities. One may try to speed up the entire classical image generation pipeline using much processing power but this would clearly lessen the advantages of raster workstations as popular, relatively inexpensive devices. This paper continues our work in restructuring the functional model (first formulated by Ingrid Carlbom) for high-performance architectures. Central to our approach is a visible concern about the underlying data structures used to represent the geometric objects. This originates from the conviction that only through careful design of appropriate graphics data structures and algorithms one can profitably map software tasks into hardware, specifically VLSI. Here we elaborate on a novel object description scheme called "pattern representation" and its envisioned usage. Our work is decidedly in contrast with several current research efforts in the area of graphics hardware where it is commonplace to simply put several processors into a cooperative effort to share the total burden, with each processor taking responsibility for part of the work.
An Exact Incremental Hidden Surface RemovalAlgorithm
(The Eurographics Association, 1987) Kuijk, A.A.M.; Hagen, P.J. W. ten; Akman, V.; Fons Kuijk and Wolfgang Strasser
This paper describes an incremental Hidden Surface Removal Algorithm (HSRA), developed to be embedded in a new architecture for raster graphics described in [1,7]. The algorithm can be classified as "exact" since it operates in object space, rather than image space. It can be classified as "incremental" because this HSRA is able to support addition, removal and changes on a single object or a group of objects. Thus a firm basis for powerful interaction and animation is established. Due to specially designed data structures for both geometriC objects as well as storage of these objects, the hidden surface removal calculation on a complete scene will have the same time complexity as existing algorithms. However, the effort needed for incremental changes is much less than any other known algorithm. The data structures as well as the algorithm are designed to exploit parallelism in computation.
Parallel Subpixel Scanconversion
(The Eurographics Association, 1987) Claussen, Ute; Fons Kuijk and Wolfgang Strasser
"IntroductionComputer graphics and its subsections image processing, image analysis and image generation are known to be a wide field for the application of parallel architectures. While in image processing and analysis the demand for ""real time"" computation is in the center of discussion, it becomes more and more important in the field of image generation, too. Some applications, like sequences of realistic appearing images raise highest demands on algorithm and architecture as well."
A Two-Dimensional Frame Buffer Processor
(The Eurographics Association, 1987) Kaufman, Arie; Fons Kuijk and Wolfgang Strasser
The two-dimensional Frame Buffer Processor (FBP) is part of a proposed raster graphics computer architecture. It is a hardware-oriented organisation of a variation of a bitblt engine with a much richer repertoire. In addition, the FBP gives support to window management, transformations, and assists in some image operations ordinarily performed in software. The introduction of the FBP as a co-processor to geometry and video processors would increase efficiency and speed of graphics systems and bitmap workstations. A special skewed frame-buffer organisation, which allows parallel memory access, further improves system performance.
A Multi-Processor Workstationwith a Logic-Enhanced Distributed Frame Buffer
(The Eurographics Association, 1987) Jansen, Frederik W.; Fons Kuijk and Wolfgang Strasser
A graphics workstation should offer both a wide variety of 20 and 3D realtime display functions as well as a programmable parallel-processing capacity for large processing tasks. A system concept is proposed that meets these requirements by offering a multi-processor configuration with general-purpose programmable processors, enhanced with specific logic that can perform for each node a large number of simple pixel operations in parallel.

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