EGGH90: Eurographics Workshop on Graphics Hardware 1990

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A Cellular Architecture for Ray Tracing
(The Eurographics Association, 1990) Atamenia, Abdelghani; Meriaux, Michel; Lepretre, Eric; Degrande, Samuel; Vidal, Bruno; Richard Grimsdale and Arie Kaufman
"We propose in this paper a massively parallel machine dedicated to image synthesis by discrete ray tracing techniques. This machine is a four-stage pipeline, the last stage being a bidimensional cellular array with one cell per pixel. Two main phases describe its behaviour: Loading into the cellular array of the objects of the scene to be displayed, after having been transformed into sets of planar polygons, and then into voxels. Cellular ray tracing over the fully distributed scene.The first phase allows us to see this machine as a massively parallel (not realistic) rendering unit: at the end of the loading phase: objects are fully identified pixel per pixel in the cellular array. Then, we have only to display the computed visual features (by means of Gouraud or Phong-like incremental methods during the loading phase).The second phase increases the image quality by executing the ray tracing algorithm in a very special way, i.e., completely distributed all over the many cells of the array. In that phase, objects are seen as split into voxels into a virtual 3D memory space. The machine is an attempt to bring a dramatic answer to the problem of performance, taking into account not only the computational power required for image synthesis by using a massive parallelism, but also the realization costs by using very regular structures, which make it a VLS1-oriented architecture."
Real Time Phong Shading
(The Eurographics Association, 1990) Claussen, Ute; Richard Grimsdale and Arie Kaufman
Nowadays, hardware support for Gouraud shading is state-of-the-art. Most hardware implementations of the Phong shading algorithm lack flexibility, for example are restricted in the number of light sources. In this paper, we will present a concept of shading processors that has been developed in a rendering system called PROOF. Two types of processors have been designed, one performing the normalization of vectors. The other one is designed for faster and cheaper shading. The capabilities of the processors are demonstrated.
A Multipurpose Hardware Shader
(The Eurographics Association, 1990) Pöpsel, Josef; Tikwinski, Eckard; Richard Grimsdale and Arie Kaufman
For the last few years the state of the art in producing three-dimensional Gouraud shaded graphics has been the use of Gouraud shading hardware. Combined with z-buffering it enables graphic workstations to provide real time display. The disadvantages of this approach are the relatively poor quality of Gouraud shaded images and its still very high cost, which so far prohibit real-time applications running on standard PCs. This article describes a universal approach to provide a very powerful graphic unit using minimal hardware at very low cost. This graphic unit will not only support Gouraud shading, but also such methods as 2D-texturing (3], solid texturing [10], normal (bump) texturing [2], shadow mapping [15, 13] and Phong shading [11] as well as a combination of these methods (shade trees [5]).
The Triangle Shading Engine
(The Eurographics Association, 1990) Ackermann, Hans-Josef; Hornung, Christoph; Richard Grimsdale and Arie Kaufman
This paper describes an algorithm implementing the Gouraud-shading of triangles and its realization in hardware. Different realizations using span shading hard ware are discussed. Their drawbacks lead to the concept of a triangle shader, designed as an ASIC. Interfaced to a signal processor for geometry computations, this chip will provide an effective and low-cost 3D-extension to graphics subsystems in the PC environment.
I.M.O.G.E.N.E.-A Solution to the Real Time Animation Problem
(The Eurographics Association, 1990) Chaillou, Christophe; Meriaux, Michel; Karpf, Sylvain; Richard Grimsdale and Arie Kaufman
Current graphics processors are very slow for displaying shaded 3D objects. A lot of work is being done in order to define faster display processors by using massive parallelism and VLSI components. Our proposal goes along this line with the supplemen tary aim of displaying images in real time, i.e., 25 or 30 times per second. We choose to design a graphics module without any working memory and thus without frame buffer. A massive parallelism over objects, and thus a pixel pipe-line, are used. Each Object Pro cessor handles one 3D object; all the processors work in a synchronous way, processing the same pixel simultaneously at pixel rate. These processors are built from very simple Elementary Processors (2 adders, 2 registers and 6 memory words) computing linear or quadratic expressions V(x,y), where (x,y) are the coordinates of a pixeL A pipelined tree made of basic operators (min, max, or, and, ... ) gathers the results given by the Ob ject Processors and makes inter-objects operations, at least hidden part elimination. Such a choice of course involves a high hardware complexity when displaying rather sim ple scenes. However, we feel that it is the price to pay for building graphics processors allowing real-time interactive animation (e.g., the graphics unit of a driving simulator).
An Efficient Parallel Ray Tracing Scheme for Highly Parallel Architectures
(The Eurographics Association, 1990) Badouel, Didier; Priol, Thierry; Richard Grimsdale and Arie Kaufman
The production of realistic image generated by computer requires a huge amount of computation and a large memory capacity. The use of highly parallel com puters allows this process to be performed faster. Distributed memory parallel computers (DMPCs), such as hypercubes or transputer-based machines, offer an attractive perfor mance/cost ratio when the load balancing has been balance and the partition of the data domain has been performed. This paper presents a parallel ray tracing algorithm for DMPC using a Shared Virtual Memory (SVM) which solves these two classical problems. This algorithm has been implemented on a hypercube iPSC/2 and results are given.
Correct Shading of Regularized CSG Solids Using a Depth-Interval Buffer
(The Eurographics Association, 1990) Rossignac, Jaroslaw R.; Wu, Jeffrey; Richard Grimsdale and Arie Kaufman
A convenient interactive design environment requires efficient facilities for shading solid models represented in CSG. Shading techniques based on boundary eval uation or ray casting that require calculations of geometric intersections are too ineffi cient for interactive graphics when eSG primitives with curved (parametric) surfaces are involved. Projective approaches, where the primitive surfaces are scan-converted using standard hardware-supported graphic functions are preferred. Since not all the points of the faces of a CSG primitive lie on the CSG solid, scan conversion must be combined with a procedure that tests the produced 3D surface-points against the original CSG ex pression. Point classifications against primitives defined by arbitrary curved boundaries may be performed, without geometric intersections, through depth-comparisons at each pixel. This approach has been implemented for the Pixel-Power machine by researchers at UNC. It deals with complex CSG trees by converting CSG expressions into sum-of product form and repeatedly scan-converting the primitives of each product. The Trickle algorithm, which considerably reduces the number of scan-conversions in the general case has been developed at IBM Research and presented elsewhere. This paper discusses sev eral recent improvements to the original Trickle algorithm. The overall algorithm has been simplified. The scan-conversion process and the point classification tests have been modified to correctly handle cases where several primitive faces coincide within an arbi trary numerical resolution. These enhancements are not only necessary for on/on cases in regularized Boolean expressions, but also for processing pairs of faces near their common edges. Finally, we point out that a simple two-pass extension of the trickle algorithm using an auxiliary shadow buffer suffices to compute directly from CSG shaded images with shadows.
Some Practical Aspects of Rendering
(The Eurographics Association, 1990) Schilling, Andreas; Richard Grimsdale and Arie Kaufman
"The scan conversion of simple primitives, e.g., vectors and triangles has been worked on in many different ways. General descriptions of algorithms often do not consider 'minor' problems, that can be difficult to solve in practical implementation. Some of these problems are addressed in the following and ways to solve them are presentedl .The paper consists of two parts. The first part deals with the scan conversion of triangles, the second part describes the implementation of two vector drawing algorithms."
A New Space Partitioning for Mapping Computations of the Radiosity Method onto a Highly Pipelined Parallel Architecture
(The Eurographics Association, 1990) Shen, Li-Sheng; Deprettere, E.; Dewilde, P.; Richard Grimsdale and Arie Kaufman
Despite the fact that realistic images can be generated by ray-tracing and radiosity shading, these techniques are impractical for scenes of high complexity because of the extremely high time cost. Several attempts have been made to reduce image synthesis time by using parallel architectures, but they still suffer from communication problems. In this paper, we present a new space partitioning which is adaptive to the local environment seen by a bundle of rays. Two tracking mechanisms are embedded to guarantee adaptation. When using a shared memory parallel architecture, the communication load between the host and the PEs can be alleviated with this approach. Furthermore, the partitioning provides a better balancing between processing throughput and I/O bandwidth which will enhance the pipelinability of computations, especially when a high speed cache memory is allowed for each PE. Combining those factors, a highly pipelined parallel architecture can be used to accelerate computations in ray-tracing and radiosity methods. The technique has been tested on different scenes with randomly generated patches in a 2D setting. When compared with the conventional technique, promising results have been observed. This technique can be easily extended to 3D.
Building a Full Scale VLSI-Based Volume Visualization System
(The Eurographics Association, 1990) Bakalash, Reuven; Kaufman, Arie; Xu, Zhong; Richard Grimsdale and Arie Kaufman
The hardware realization of an advanced prototype of the Cube volume visualization system, Cube-3, is presented. The primary hardware component of Cube is a viewing and rendering multiprocessor with distributed 3D voxel memory. Cube-3 design is based on our experience with two earlier prototypes: Cube-1 realized in hard ware using printed circuit board technology and Cube-2 our first custom-designed VLSI implementation. Both prototypes are of reduced-size resolution (163 ) and can generate only orthographic views. Cube-3 is the next generation prototype of a full-scale resolution of 2563 voxels. It has been functionally extended to generate non-orthographic projec tions, 3D real-time transformations, and shading. The ability to project and manipulate volumetric images in real-time is attributed to a unique skewed memory organization, a generalized skewed mapping, a special ray projection bus, a congradient shading tech nique, and a new barrel-shifting mechanism. This paper specifically describes the latter mechanism.
The AIDA Display Processor System Architecture
(The Eurographics Association, 1990) Evans, S. R.; Grimsdale, R. 1.; Lister, P. F.; Nimmo, A. D.; Richard Grimsdale and Arie Kaufman
This paper describes the Advanced Image Display Architecture, AIDA. The primary aims were to design a graphics display subsystem capable of satisfying the needs of both high performance workstations and vehicle simulator visual systems. AIDA can accept planar triangle primitives which have been transformed, clipped and projected by preceding stages. The system implements many desirable features including modularity, anti-aliasing, translucency, pixel-rate hidden surface removal and Gouraud shading. AIDA has been designed to take advantage of ASIC technology in the implementation of its processing units.
MARTI-A Multiprocessor Architecture for Ray Tracing Images
(The Eurographics Association, 1990) Hebert, M-P.; McNeill, M. D. J.; Shah, B.; Grimsdale, R. 1.; Lister, P. F.; Richard Grimsdale and Arie Kaufman
Multiprocessor systems are well suited to ray tracing, since each ray can be traced independently. However, the large databases required to model complex scenes create problems of data access. In this paper we propose a multiprocessor architecture for ray tracing which removes the need for duplication of the database at processor level. The database is held on a group processor basis, and resides in shared memory. Many of these groups, or clusters, can be replicated to form a highly parallel multiprocessing system. Results of a software simulation of the architecture are promising, indicating that a large number of processors per cluster is possible.

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