EGGH96: Eurographics Workshop on Graphics Hardware 1996

Permanent URI for this collection

https://diglib7.eg.org/handle/10.2312/339

Design Principles of Hardware-based Phong Shading and Bump Mapping

[meta data] [files:
003-009.pdf
]
Bennebroek, K.
; 
Ernst, I.
; 
Rüsseler, H.
; 
Wittig, O.

TAYRA - A 3D Graphics Raster Processor

[meta data] [files:
011-023.pdf
]
Waller, Marcus
; 
Dunnett, Graham
; 
Bassett, Mike
; 
MCCann, Shaun
; 
Makris, Alex
; 
White, Martin
; 
Lister, Paul

An Advanced 3D Frame Buffer Memory Controller

[meta data] [files:
025-037.pdf
]
Makris, "Alex
; 
White, Martin
; 
Lister", Paul

Optimal Static 2-Dimensional Screen Subdivision for Parallel Rasterization Architectures

[meta data] [files:
059-067.pdf
]
McManus, Donald
; 
Beckmann, Carl

The Setup for Triangle Rasterization

[meta data] [files:
049-058.pdf
]
Kugler, Anders

An Architecture for High-Performance 2-D Image Display

[meta data] [files:
039-045.pdf
]
Jordan, Stephen D.
; 
Jensen, Philip E.
; 
Lichtenbelt, Barthold B. A.

Graphics Algorithms on Field Programmable Function Arrays

[meta data] [files:
103-108.pdf
]
Smit, Jaap
; 
Bosma, Marco

On the energy complexity of Algorithms realized in CMOS, a Graphics Example

[meta data] [files:
093-101.pdf
]
Smit, J.
; 
Bosma, M.

The ImageSwitcher: A Proposed System Architecture Designed to Reduce VR Lag

[meta data] [files:
071-077.pdf
]
Banks, David C.

New advances in Neuro -Visual Simulation and Symbolic extraction for Real World Computing, 3D Image Analysis and 3D object Digitization

[meta data] [files:
079-089.pdf
]
Leray, P.

Evaluation of a Real-Time Direct Volume Rendering System

[meta data] [files:
121-131.pdf
]
Boer, M. de
; 
Hesser, J.
; 
Gropl, A.
; 
Gunther, T.
; 
Poliwoda, C.
; 
Reinhart, C.
; 
Manner, R.

Latency- and Hazard-Free Volume Memory Ar­ chitecture for Direct Volume Rendering

[meta data] [files:
109-119.pdf
]
Boer, M. de
; 
Gropl, A.
; 
Hesser, J.
; 
Männer, R.

Cube-4 Implementations on the Teramac Custom Computing Machine

[meta data] [files:
133-143.pdf
]
Kanus, Urs
; 
Meißner, Michael
; 
Straßer, Wolfgang
; 
Pfister, Hanspeter
; 
Kaufman, Arie
; 
Amerson, Rick
; 
Carter, Richard J.
; 
Culbertson, Bruce
; 
Kuekes, Phil
; 
Snider, Greg

BibTeX (EGGH96: Eurographics Workshop on Graphics Hardware 1996)
@inproceedings{
10.2312:EGGH/EGGH96/003-009,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Bengt-Olaf Schneider and Andreas Schilling
},
title = {{
Design Principles of Hardware-based Phong Shading and Bump Mapping}},

author = {
Bennebroek, K.
 and 
Ernst, I.
 and 
Rüsseler, H.
 and 
Wittig, O.
},
year = {
1996},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
10.2312/EGGH/EGGH96/003-009}

}
@inproceedings{
10.2312:EGGH/EGGH96/011-023,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Bengt-Olaf Schneider and Andreas Schilling
},
title = {{
TAYRA - A 3D Graphics Raster Processor}},

author = {
Waller, Marcus
 and 
Dunnett, Graham
 and 
Bassett, Mike
 and 
MCCann, Shaun
 and 
Makris, Alex
 and 
White, Martin
 and 
Lister, Paul
},
year = {
1996},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
10.2312/EGGH/EGGH96/011-023}

}
@inproceedings{
10.2312:EGGH/EGGH96/025-037,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Bengt-Olaf Schneider and Andreas Schilling
},
title = {{
An Advanced 3D Frame Buffer Memory Controller}},

author = {
Makris, "Alex
 and 
White, Martin
 and 
Lister", Paul
},
year = {
1996},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
10.2312/EGGH/EGGH96/025-037}

}
@inproceedings{
10.2312:EGGH/EGGH96/059-067,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Bengt-Olaf Schneider and Andreas Schilling
},
title = {{
Optimal Static 2-Dimensional Screen Subdivision for Parallel Rasterization Architectures}},

author = {
McManus, Donald
 and 
Beckmann, Carl
},
year = {
1996},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
10.2312/EGGH/EGGH96/059-067}

}
@inproceedings{
10.2312:EGGH/EGGH96/049-058,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Bengt-Olaf Schneider and Andreas Schilling
},
title = {{
The Setup for Triangle Rasterization}},

author = {
Kugler, Anders
},
year = {
1996},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
10.2312/EGGH/EGGH96/049-058}

}
@inproceedings{
10.2312:EGGH/EGGH96/039-045,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Bengt-Olaf Schneider and Andreas Schilling
},
title = {{
An Architecture for High-Performance 2-D Image Display}},

author = {
Jordan, Stephen D.
 and 
Jensen, Philip E.
 and 
Lichtenbelt, Barthold B. A.
},
year = {
1996},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
10.2312/EGGH/EGGH96/039-045}

}
@inproceedings{
10.2312:EGGH/EGGH96/103-108,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Bengt-Olaf Schneider and Andreas Schilling
},
title = {{
Graphics Algorithms on Field Programmable Function Arrays}},

author = {
Smit, Jaap
 and 
Bosma, Marco
},
year = {
1996},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
10.2312/EGGH/EGGH96/103-108}

}
@inproceedings{
10.2312:EGGH/EGGH96/093-101,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Bengt-Olaf Schneider and Andreas Schilling
},
title = {{
On the energy complexity of Algorithms realized in CMOS, a Graphics Example}},

author = {
Smit, J.
 and 
Bosma, M.
},
year = {
1996},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
10.2312/EGGH/EGGH96/093-101}

}
@inproceedings{
10.2312:EGGH/EGGH96/071-077,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Bengt-Olaf Schneider and Andreas Schilling
},
title = {{
The ImageSwitcher: A Proposed System Architecture Designed to Reduce VR Lag}},

author = {
Banks, David C.
},
year = {
1996},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
10.2312/EGGH/EGGH96/071-077}

}
@inproceedings{
10.2312:EGGH/EGGH96/079-089,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Bengt-Olaf Schneider and Andreas Schilling
},
title = {{
New advances in Neuro -Visual Simulation and Symbolic extraction for Real World Computing, 3D Image Analysis and 3D object Digitization}},

author = {
Leray, P.
},
year = {
1996},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
10.2312/EGGH/EGGH96/079-089}

}
@inproceedings{
10.2312:EGGH/EGGH96/121-131,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Bengt-Olaf Schneider and Andreas Schilling
},
title = {{
Evaluation of a Real-Time Direct Volume Rendering System}},

author = {
Boer, M. de
 and 
Hesser, J.
 and 
Gropl, A.
 and 
Gunther, T.
 and 
Poliwoda, C.
 and 
Reinhart, C.
 and 
Manner, R.
},
year = {
1996},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
10.2312/EGGH/EGGH96/121-131}

}
@inproceedings{
10.2312:EGGH/EGGH96/109-119,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Bengt-Olaf Schneider and Andreas Schilling
},
title = {{
Latency- and Hazard-Free Volume Memory Ar­ chitecture for Direct Volume Rendering}},

author = {
Boer, M. de
 and 
Gropl, A.
 and 
Hesser, J.
 and 
Männer, R.
},
year = {
1996},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
10.2312/EGGH/EGGH96/109-119}

}
@inproceedings{
10.2312:EGGH/EGGH96/133-143,

booktitle = {
Eurographics Workshop on Graphics Hardware},

editor = {
Bengt-Olaf Schneider and Andreas Schilling
},
title = {{
Cube-4 Implementations on the Teramac Custom Computing Machine}},

author = {
Kanus, Urs
 and 
Meißner, Michael
 and 
Straßer, Wolfgang
 and 
Pfister, Hanspeter
 and 
Kaufman, Arie
 and 
Amerson, Rick
 and 
Carter, Richard J.
 and 
Culbertson, Bruce
 and 
Kuekes, Phil
 and 
Snider, Greg
},
year = {
1996},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
10.2312/EGGH/EGGH96/133-143}

}

Browse

Recent Submissions

Now showing 1 - 13 of 13
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    Design Principles of Hardware-based Phong Shading and Bump Mapping
    (The Eurographics Association, 1996) Bennebroek, K.; Ernst, I.; Rüsseler, H.; Wittig, O.; Bengt-Olaf Schneider and Andreas Schilling
    The VISA+ hardware architecture is the first of a new generation of graphics accelerators designed primarily to render bump-, texture-, environment- and environment-bump-mapped polygons. This paper presents examples of the main graphical capabilities and discusses methods and simplifications used to create high quality images. One of the key concepts in the VISA+ design, the use of reflectance cubes, is predestined for environment mapping. In combination with bump- and texture­ mapping it shows the strength of our new architecture. Furthermore it justifies some of the decision's made duringsimulation and development of the complex VISA+ architecture.
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    TAYRA - A 3D Graphics Raster Processor
    (The Eurographics Association, 1996) Waller, Marcus; Dunnett, Graham; Bassett, Mike; MCCann, Shaun; Makris, Alex; White, Martin; Lister, Paul; Bengt-Olaf Schneider and Andreas Schilling
    This paper describes the Junctionality oj a 3D Graphics Raster Processor called TAYRA. TAYRA consists in the most part oj Graphics Raster Pipeline with five major external interfaces: PCI Master/Target, Depth, Texture, Colour and Video Interfaces.The Graphics Raster Pipeline perform'S' all the major OpenGL style (not necessarily compliant) raster functions: scan conversion; lines, spans, triangles, rectangles, perspective correction o f texture coordinates. mip map jevel selection, and many other texture modes, alpha blending, and other Junctionalities. Further, through TAYRA's fast host to buffer access mechanisms it can do advanced stencilling, multi-pass antialiasing, and other algorithms; all accelerated in hardware with a sustained pixel write speed of 29 MPixels/sec (peak of 33 MPixels/sec). This translates to a peak 25 pixel triangle drawing speed of 890K Triangles/sec, limited bv PCI bus bandwidth.
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    An Advanced 3D Frame Buffer Memory Controller
    (The Eurographics Association, 1996) Makris, "Alex; White, Martin; Lister", Paul; Bengt-Olaf Schneider and Andreas Schilling
    This paper details the design o f an advanced 32 bit 3D frame buffer memory controller for a 3D Graphics Raster Processor called TAYRA [1]. This memory controller is designed to provide a performance o f 33 MPixelsls for read and write cycles, 4 GPixelsls for block write, and 16.5 MPixelsls for read, modify, write cycles (with a pixel size o f 4 bytes). This performance is without any interleaving. It has several control modes: S3 shared frame buffer protocol compatibility [2], stand alone 3D buffers, multiplexed 2DI3D buffers, and others. Further, our 3D memory controller is designed to control DRAM, VRAM and WRAM, and EDO versions of these memories. Also, we support up to 4 screen buffers, 16 MBytes o f screen memory, and many combinations o f memory organisationsup to 1600x1280.
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    Optimal Static 2-Dimensional Screen Subdivision for Parallel Rasterization Architectures
    (The Eurographics Association, 1996) McManus, Donald; Beckmann, Carl; Bengt-Olaf Schneider and Andreas Schilling
    Designers of computer graphics hardware have used increasing device counts available from IC manufacturers to increase parallelism using techniques such as putting a longer pipeline of data path elements on integrated circuits or developing designs which use an array of processors. Pixel-Planes 1-5 and PixelFIowl are examples of architectures which use an array of pixel processors for rasterization. Early generations of Pixel­ Planes attempted to make these arrays as large as the display providing one processor for each display pixel. Later generations improved performance by grouping processors into multiple smaller arrays, subdividing the screen into sections of a corresponding size and having the arrays independently process the screen subdivisions. This paper describes'simulations which were performed to determine the optimum size subdivision for a graphics computer which uses Pixel-Planes type parallelism. i.e. static. two dimensional screen subdivision parallel polygon rastenzation. We then develop a mathematical approach to determining the optimal subdivision size and show that it agrees well with the experimental data. For special purpose architectures we show that the optimal size depends not only on the polygon size but also on the silicon area consumed by the rasterizer overhead. The mathematical approach can be directly applied to special purpose architectures. and we show how it can be modified for use in analyzing algorithms developed for general purpose architectures such as the Intel Touchstone or Paragon or the Thinking Machines CM-5.
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    The Setup for Triangle Rasterization
    (The Eurographics Association, 1996) Kugler, Anders; Bengt-Olaf Schneider and Andreas Schilling
    Integrating the slope and setup calculationsfor triangles to the rasterizer offloads the host processor from intensive calculations and can significantly increase 3D system performance. The processing on the host is greatly reduced and much less data is passed from the host to the graphics subsystem. A setup architecture handling generalized triangle meshes and computing all necessary parameters for a high-end raster pipe­line to generate Gouraud shaded, texture- and bump­mapped triangles is described and its benefits on the final bandwidth are shown. To efficiently compute the slopes and color gradients for each triangle, some implementation aspects on division and multiplicationpipelines are discussed.
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    An Architecture for High-Performance 2-D Image Display
    (The Eurographics Association, 1996) Jordan, Stephen D.; Jensen, Philip E.; Lichtenbelt, Barthold B. A.; Bengt-Olaf Schneider and Andreas Schilling
    Image processing operations can be divided into two classes, those pre-processing operations that are market- and application-specific, and those widely-used operations that are useful in any application that requires the display of two-dimensional images. In the interest of achieving real-time rates for the broader class of 2-D image display operations, Hewlett-Packard has developed a hardware accel­ erator called VISUALIZE-IVX. It is capable of scaling, rotating, mirroring, translating and filtering lk-by-lk output images at greater than 30 frames/sec while simultaneously enhancing image brightness and contrast. This paper describes the pipelined architecture u.sed to'actiieve this performance oh a desktop computer. The Architecture makes use of a hybrid mapping scheme for geometric transformations. Also a unique memory device was designed that minimizes local image buffers while eliminating the need to resend pixels from main memory. A recently developed method of extending the filtering capabilities, that may be incorporated into future products, is also presented.
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    Graphics Algorithms on Field Programmable Function Arrays
    (The Eurographics Association, 1996) Smit, Jaap; Bosma, Marco; Bengt-Olaf Schneider and Andreas Schilling
    The amount of energy consumed in basic CMOS building blocks, like external RAM, external bus-structures, multipliers, local (cache) memory and on chip bus-structures, is analyzed thoroughly to find ways for substantial improvement of the power consumption of high speed graphics algorithms: A Field Programmable Function Array capable of low-power execution of a wide range of algorithms is introduced. Aspects of the compilation of the volume rendering algorithm to this architecture are discussed.
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    On the energy complexity of Algorithms realized in CMOS, a Graphics Example
    (The Eurographics Association, 1996) Smit, J.; Bosma, M.; Bengt-Olaf Schneider and Andreas Schilling
    A theory about the energy consumption of algorithms realized in CMOS, presented in related work, makes it possible to calculate the minimal amount of energy dissipated for the execution of an algorithm. The rendering of a dense dataset with three variants of the Volume Rendering algorithm wi11 be considered as an example of the methodology. The absolute lower bound of the energy consumption is calculated for the rendering of a dense 256"3 dataset using implementations of the algorithms in an 1um CMOS process. Predictions of the energy consumption in future CMOS generations are given as well.
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    The ImageSwitcher: A Proposed System Architecture Designed to Reduce VR Lag
    (The Eurographics Association, 1996) Banks, David C.; Bengt-Olaf Schneider and Andreas Schilling
    Latency contributes to image error and to motion sickness in head­ tracked graphics displays. We attack the problem of latency by exploiting parallel scene generation, using multiple graphics engines to render images corresponding to a cloud of viewpoints. The real-time position of a 3D tracker is used to select among several just-generated images, rather than to generate a new image, for each frame. The system's scalable architecture is comprised of off-the-shelf components. When. future PC-class machines offer inexpensive high-speed 3D graphics, the design of the system will become economically attractive.
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    New advances in Neuro -Visual Simulation and Symbolic extraction for Real World Computing, 3D Image Analysis and 3D object Digitization
    (The Eurographics Association, 1996) Leray, P.; Bengt-Olaf Schneider and Andreas Schilling
    3D image analysis and automatic modelling using Neurofocalisation and attractiveness with hardwarefilters. Towards a new kind of filter-based data structures instead of splines/polygons.
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    Evaluation of a Real-Time Direct Volume Rendering System
    (The Eurographics Association, 1996) Boer, M. de; Hesser, J.; Gropl, A.; Gunther, T.; Poliwoda, C.; Reinhart, C.; Manner, R.; Bengt-Olaf Schneider and Andreas Schilling
    VIRIM, a real-time direct volume rendering system is evaluated for medical applications. Experiences concerning the hardware architecture are discussed. The issues are the flexibility of VIRIM, the restriction to two gradient components only, the duplication of the volume data sets on different modules, the size of the volume data set, the gray-value segmentation tool, and the support of algorithmic improvements like space- leaping, early ray-termination and others.It turned out that flexibility is the main benefit and absolutely necessary for VIRIM. Given this flexibility the application areas of real-time rendering systems increase dramatically: Most of the user requirements focus now not on visualization but on general volume data processing. The most serious bot­ tleneck of VIRIM is the limited volume memory that is inte­ grated on the first prototype.
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    Latency- and Hazard-Free Volume Memory Ar­ chitecture for Direct Volume Rendering
    (The Eurographics Association, 1996) Boer, M. de; Gropl, A.; Hesser, J.; Männer, R.; Bengt-Olaf Schneider and Andreas Schilling
    The computational power required for direct volume rendering like ray-casting or volume ray-tracing can be provided by high­ speed rendering architectures. However the increasing proces­ sor speed makes a performance bottleneck obvious - the vol­ ume memory. This paper describes a volume memory architec­ ture that achieves at least a tenfold speed-up in read-out rate with moderate additional hardware. It has been simulated suc­ cessfully. A multi-level cache system is used with software prefetching and latency hiding. Pre- and postcaches addi­ tionally speed up the read-out rate so that a 5123 data set stored in a single memory module can be rendered at 3.125 Hz.
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    Cube-4 Implementations on the Teramac Custom Computing Machine
    (The Eurographics Association, 1996) Kanus, Urs; Meißner, Michael; Straßer, Wolfgang; Pfister, Hanspeter; Kaufman, Arie; Amerson, Rick; Carter, Richard J.; Culbertson, Bruce; Kuekes, Phil; Snider, Greg; Bengt-Olaf Schneider and Andreas Schilling
    We present two implementations of the Cube-4 volume rendering architecture on the Teramac custom computing machine. Cube-4 uses a slice­ parallel ray-casting algorithm that allows for a paral­ lel and pipelined implementation of ray-casting with tri-linear interpolation and surface normal estimation from interpolated samples. Shading, classification and compositing are part of rendering pipeline. With the partitioning schemes introduced in this paper, Cube-4 is capable of rendering large datasets with a limited number of pipelines. The Teramac hardware simulator at the Hewlett-Packard research laboratories, Palo Alto, CA, on which Cube-4 was implemented, belongs to the new class of custom computing machines. Teramac combines the speed of special-purpose hardware with the flexibility of general-purpose computel's. With Teramac as a development tool we were able to implement in just five weeks working Cube-4 prototypes, capable of rendering for example datasets of 1283 voxels in 0.65 seconds at 0,96 MHz processing frequency. The performance results from these implementations indicate real-time performance for high-resolution data-sets.